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publication number s71ws512/256nx0_ut revision a amendment 0 issue date november 8, 2004 advance information s71ws512nx0/s71ws256nx0 based mcps stacked multi-chip product (mcp) 256/512 megabit (32m/16m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with 128 megabit (8m x 16-bit) psram type 4 distinctive characteristics mcp features ? power supply voltage of 1.7 to 1.95v ? burst speed: 54mhz ? packages: 8 x 11.6 mm, 9 x 12 mm ? operating temperature ? -25c to +85c ? -40c to +85c general description the s71ws series is a product line of stacked multi-chip product (mcp) packages and consists of ? one or more flash memory die ? psram type 4?compatible psram the products covered by this document are listed in the table below. for details about their specifications, please refer to the individual constituent datasheet for further details. flash density 512mb 256mb 128mb 64mb psram density 128mb s71ws512nd0 s71ws256nd0 64mb 32mb 16mb
november 8, 2004 s71ws512/256nx0_uta0 s71ws512nx0/s71ws256nx0 2 advance information s71ws512nx0/s71ws256nx0 based mcps distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ................................................................................................... 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 bproduct selector guide . . . . . . . . . . . . . . . . . . . . .5 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . .6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .7 type 4 - based pinout ..........................................................................................7 mcp look-ahead connection diagram .........................................................8 input/output descriptions . . . . . . . . . . . . . . . . . . . .9 ordering information . . . . . . . . . . . . . . . . . . . . . . . 10 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . 11 256mb - ws256n flash + 128 psram .......................................................... 11 2x256mb?ws256n flash + 128mb psram ............................................... 11 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12 fea084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 mm mcp compatible package ........................................................................................... 12 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 mm mcp compatible package ............................................................................................13 tla084?84-ball fine-pitch ball grid array (fbga) 11.6x8.0x1.2 mm mcp compatible package ................................................................................14 s29wsxxxn mirrorbit? flash family general description . . . . . . . . . . . . . . . . . . . . . . . 15 application notes ........................................................................................... 18 specification bulletins .................................................................................... 18 drivers and software support .................................................................... 18 cad modeling support ................................................................................ 18 technical support ........................................................................................... 18 spansion llc locations ........................................................ 18 table 4.2. s29ws128n sector & memory address map .......... 20 table 4.3. s29ws064n sector & memory address map .......... 21 table 5.4. device operations .............................................. 22 table 5.7. address latency for 5 wait states ( 68 mhz) ........ 24 table 5.8. address latency for 4 wait states ( 54 mhz) ........ 25 table 5.9. address latency for 3 wait states ( 40 mhz) ........ 25 table 5.10. address/boundary crossing latency for 6 wait states ( 80 mhz) ....................................................................... 25 table 5.11. address/boundary crossing latency for 5 wait states ( 68 mhz) ....................................................................... 25 table 5.12. address/boundary crossing latency for 4 wait states ( 54 mhz) ....................................................................... 25 table 5.13. address/boundary crossing latency for 3 wait states ( 40 mhz) ....................................................................... 25 figure 5.2. synchronous read ............................................. 26 table 5.14. burst address groups ....................................... 27 table 5.15. configuration register ....................................... 28 table 5.16. autoselect addresses ........................................ 29 table 5.17. autoselect entry ............................................... 29 table 5.18. autoselect exit ................................................. 30 figure 5.19. single word program ........................................ 32 table 5.20. single word program ........................................ 33 table 5.21. write buffer program ........................................ 35 figure 5.22. write buffer programming operation .................. 36 table 5.23. sector erase .................................................... 38 figure 5.24. sector erase operation ..................................... 39 table 5.25. chip erase ....................................................... 40 table 5.26. erase suspend ................................................. 41 table 5.27. erase resume .................................................. 41 table 5.28. program suspend ............................................. 42 table 5.29. program resume .............................................. 42 table 5.30. unlock bypass entry .......................................... 43 table 5.31. unlock bypass program ..................................... 44 table 5.32. unlock bypass reset ......................................... 44 figure 5.33. write operation status flowchart....................... 46 table 5.34. dq6 and dq2 indications ................................... 48 table 5.35. write operation status ...................................... 49 table 5.36. reset .............................................................. 51 figure 6.2. lock register program algorithm......................... 57 table 8.2. secsi sector entry .............................................. 63 table 8.3. secsi sector program .......................................... 64 table 8.4. secsi sector entry .............................................. 64 figure 9.2. maximum positive overshoot waveform ............... 65 figure 9.3. test setup........................................................ 66 figure 9.4. input waveforms and measurement levels ........... 67 figure 9.5. v cc power-up diagram....................................... 67 figure 9.6. clk characterization.......................................... 69 figure 9.7. clk synchronous burst mode read...................... 71 figure 9.8. 8-word linear burst with wrap around ................. 72 figure 9.9. 8-word linear burst without wrap around ............ 72 figure 9.10. linear burst with rdy set one cycle before data 73 figure 9.11. asynchronous mode read ................................. 74 figure 9.12. reset timings ................................................. 75 figure 9.2. chip/sector erase operation timings: we# latched addresses......................................................................... 77 figure 9.13. asynchronous program operation timings: we# latched addresses............................................................. 78 figure 9.14. synchronous program operation timings: clk latched addresses ...................................................... 79 figure 9.15. accelerated unlock bypass programming timing .. 80 figure 9.16. data# polling timings (during embedded algorithm) ............................................. 80 figure 9.17. toggle bit timings (during embedded algorithm) 81 figure 9.18. synchronous data polling timings/toggle bit timings ................................................. 81 figure 9.19. dq2 vs. dq6................................................... 82 figure 9.20. latency with boundary crossing when frequency > 66 mhz.......................................................... 82 figure 9.21. latency with boundary crossing into program/ erase bank ....................................................................... 83 figure 9.22. example of wait states insertion ....................... 84 figure 9.23. back-to-back read/write cycle timings.............. 85 table 10.2. sector protection commands .............................. 90 table 10.3. cfi query identification string ............................ 91 table 10.4. system interface string ..................................... 92 table 10.5. device geometry definition ................................ 92 table 10.6. primary vendor-specific extended query ............. 93 psram type 4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 99 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . 100 power up ............................................................................................................ 100 figure 11.24. power up timing.......................................... 100 standby mode .................................................................................................... 100 figure 11.25. standby mode state machines ....................... 100 functional description . . . . . . . . . . . . . . . . . . . . . 101 table 11.7. asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) ............................................................... 101 table 11.8. synchronous burst read & asynchronous write mode (a15/a14=0/1) ............................................................... 102 table 11.9. synchronous burst read & synchronous burst write mode(a15/a14=1/0) ........................................................ 103 mode register setting operation . . . . . . . . . . . . 103
3 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_uta0 november 8, 2004 advance information mode register set (mrs) ...............................................................................104 table 11.10. mode register setting according to field of function ...............................................................104 table 11.11. mode register set ..........................................104 mrs pin control type mode register setting timing .......................... 105 figure 11.26. mode register setting timing (oe# = v ih ) ...... 106 table 11.12. mrs ac characteristics ...................................106 asynchronous operation . . . . . . . . . . . . . . . . . . 107 asynchronous 4 page read operation ...................................................... 107 asynchronous write operation .................................................................. 107 asynchronous write operation in synchronous mode ....................... 107 figure 11.27. asynchronous 4-page read............................ 107 figure 11.28. asynchronous write ...................................... 107 synchronous burst operation . . . . . . . . . . . . . . 108 synchronous burst read operation ...........................................................108 synchronous burst write operation .........................................................108 figure 11.29. synchronous burst read................................ 108 figure 11.30. synchronous burst write ............................... 109 synchronous burst operation terminology . . 109 clock (clk) ........................................................................................................109 latency count ....................................................................................................109 table 11.13. latency count support ...................................109 table 11.14. number of clocks for 1st data ........................109 figure 11.31. latency configuration (read) ......................... 110 burst length ........................................................................................................110 burst stop .............................................................................................................110 synchronous burst operation terminology . . . 110 wait control (wait#) ...................................................................................110 figure 11.32. wait# and read/write latency control........... 111 burst type ............................................................................................................. 111 table 11.15. burst sequence .............................................111 low power features . . . . . . . . . . . . . . . . . . . . . . 112 internal tcsr ...................................................................................................... 112 figure 11.33. par mode execution and exit ......................... 112 table 11.16. par mode characteristics ................................112 driver strength optimization ........................................................................ 112 partial array refresh (par) mode ............................................................... 112 absolute maximum ratings . . . . . . . . . . . . . . . . . 113 dc recommended operating conditions . . . . . 113 capacitance (ta = 25c, f = 1 mhz) . . . . . . . . . . 113 dc and operating characteristics . . . . . . . . . . . 114 common ............................................................................................................... 114 ac operating conditions . . . . . . . . . . . . . . . . . . 115 test conditions (test load and test input/output reference) ........ 115 figure 11.34. output load................................................. 115 asynchronous ac characteristics ............................................................... 116 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 117 asynchronous read timing waveform ...................................................... 117 figure 11.35. timing waveform of asynchronous read cycle 117 table 11.17. asynchronous read ac characteristics .............117 page read .........................................................................................................118 figure 11.36. timing waveform of page read cycle ............. 118 table 11.18. asynchronous page read ac characteristics ......118 asynchronous write timing waveform .................................................... 119 figure 11.37. timing waveform of write cycle .................... 119 table 11.19. asynchronous write ac characteristics .............119 write cycle 2 ................................................................................................ 120 figure 11.38. timing waveform of write cycle(2)................. 120 table 11.20. asynchronous write ac characteristics (ub# & lb# controlled) ......................................................................120 write cycle (address latch type) .......................................................... 121 figure 11.39. timing waveform of write cycle (address latch type)............................................................................. 121 table 11.21. asynchronous write in synchronous mode ac characteristics ................................................................ 121 asynchronous write timing waveform in synchronous mode ........122 write cycle (low adv# type) ...............................................................122 figure 11.40. timing waveform of write cycle (low adv# type).................................................... 122 table 11.22. asynchronous write in synchronous mode ac characteristics ................................................................ 122 write cycle (low adv# type) ............................................................... 123 figure 11.41. timing waveform of write cycle (low adv# type) ............................................................ 123 table 11.23. asynchronous write in synchronous mode ac characteristics ................................................................ 123 multiple write cycle (low adv# type) ..............................................124 figure 11.42. timing waveform of multiple write cycle (low adv# type)............................................................................. 124 table 11.24. asynchronous write in synchronous mode ac characteristics ................................................................ 125 ac operating conditions . . . . . . . . . . . . . . . . . . 126 test conditions (test load and test input/output reference) ........126 figure 11.43. ac output load circuit ................................. 126 table 11.25. synchronous ac characteristics ..................... 127 synchronous burst operation timing waveform . . . . . . . . . . . . . . . . . . . . . . . 128 figure 11.44. timing waveform of basic burst operation ..... 128 table 11.26. burst operation ac characteristics .................. 128 synchronous burst read timing waveform . . . 129 read timings .......................................................................................................129 figure 11.45. timing waveform of burst read cycle (1) ....... 129 table 11.27. burst read ac characteristics ......................... 130 figure 11.46. timing waveform of burst read cycle (2) ....... 130 table 11.28. burst read ac characteristics ......................... 131 figure 11.47. timing waveform of burst read cycle (3) ....... 131 table 11.29. burst read ac characteristics ......................... 132 write timings ..................................................................................................... 133 figure 11.48. timing waveform of burst write cycle (1)....... 133 table 11.30. burst write ac characteristics ........................ 134 figure 11.49. timing waveform of burst write cycle (2)....... 135 table 11.31. burst write ac characteristics ........................ 135 synchronous burst read stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 11.50. timing waveform of burst read stop by cs# .. 136 table 11.32. burst read stop ac characteristics ................. 136 synchronous burst write stop timing waveform . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 11.51. timing waveform of burst write stop by cs#.. 137 table 11.33. burst write stop ac characteristics ................. 137 synchronous burst read suspend timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 11.52. timing waveform of burst read suspend cycle (1) ................................................... 138 table 11.34. burst read suspend ac characteristics ............ 138 transition timing waveform between read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 11.53. synchronous burst read to asynchronous write (address latch type) ....................................................... 139 table 11.35. burst read to asynchronous write (address latch type) ac characteristics ................................................... 139 figure 11.54. synchronous burst read to asynchronous write (low adv# type).................................................................... 140 table 11.36. burst read to asynchronous write (low adv# type)
november 8, 2004 s71ws512/256nx0_uta0 s71ws512nx0/s71ws256nx0 4 advance information ac characteristics ............................................................140 figure 11.55. asynchronous write (address latch type) to synchronous burst read timing ......................................... 141 table 11.37. asynchronous write (address latch type) to burst read ac characteristics ....................................................141 figure 11.56. asynchronous write (low adv# type) to synchronous burst read timing ......................................... 142 table 11.38. asynchronous write (low adv# type) to burst read ac characteristics ............................................................142 figure 11.57. synchronous burst read to synchronous burst write timing ........................................................................... 143 table 11.39. asynchronous write (low adv# type) to burst read ac characteristics ............................................................ 143 figure 11.58. synchronous burst write to synchronous burst read timing ........................................................................... 144 table 11.40. asynchronous write (low adv# type) to burst read ac characteristics ............................................................ 144 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 146
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 5 product selector guide ws256n + 128 psram ws512n + 128 psram device-model psram density flash speed mhz psram speed mhz dyb bits - power up supplier package s71ws256nd0-e3 128m 54 54 0 (protected) type 4 tsd084 9x12x1.2 s71ws256nd0-e7 1 (unprotected [default state]) device-model psram density flash speed mhz psram speed mhz dyb bits - power up supplier package s71ws512nd0-y3 128mb 54 54 0 1.8v ram type 4 fea084 9x12x1.4 s71ws512nd0-y7 1
6 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_ut november 8, 2004 mcp block diagram notes: 1. for 1 flash + psram, f1-ce# = ce#. for 2 flash + psram, ce# = f1-ce# and f2-ce# is the chip-enable pin for the second flash. 2. only needed for s71ws512n. 3. for the 128m psram devices, there are 23 shared addresses. v id v cc rdy psram flash 1 dq15 to dq0 flash-only address shared address (note 3) f1-ce# acc r-ub# r-vcc v cc v ccq f-vcc 22 clk clk wp# oe# we# f-rst# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 r-ce1# ce# we# oe# ub# r-lb# lb# 22 (note 3) f2-ce# clk avd# flash 2 (note 4) wait# r-mrs mrs
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 7 connection diagrams type 4 - based pinout notes: 1. in mcp's based on a single s29ws256n (s71ws256n), ball b5 is rfu. in mcp's based on two s29ws256n (s71ws512), ball b5 is or f2-ce#. 2. addresses are shared between flash and ram depending on the density of the psram. mcp flash-only addresses shared addresses s71ws256nc0 a23-a22 a21-a0 s71ws512nd0 a23 a22-a0 a7 a3 a2 dq8 dq14 r-ce1# r-lb# f-acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 rdy a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 r-mrs h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-v cc r-v cc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu clk f2-ce# rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-v cc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 avd# rfu rfu rfu rfu f-wp# rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu ram only shared flash xip only legend reserved for future use 2nd flash only 1st flash only 84-ball fine-pitch ball grid array type 4-based pinout (top view, balls facing down)
8 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_ut november 8, 2004 mcp look-ahead connection diagram notes: 1. in a 3.0v system, the gl device used as data has to have wp tied to vcc. 2. f1 and f2 denote xip/flash, f3 and f4 denote data/companion flash. j4 j5 j6 j7 j8 j9 h7 h8 h9 f7 f7 f8 f8 f9 f9 e7 e8 e9 d5 k3 k3 d6 d7 f1-ce# j3 oe# r1-ce1# dq0 d2 d3 c2 c3 avd# vss see table a7 a8 we# d-dm0/ d1, d# c4 c5 c6 c7 d8 d9 f3-ce# a11 c8 c9 f2-oe# r-oe# f-clk# f-vcc f2-ce# clk a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 a24 dq6 h6 f6 f6 r1-ce2 a20 a23 r2-ce2 h4 h4 h5 g5 f4 f4 f5 f5 e5 f-rst# see table a18 r2-ce1 a17 r2-vcc dq1 r-cre dq15 dq13 dq4 dq3 dq9 k4 k4 k7 k7 k8 k8 k9 k9 dq7 r1-vcc f-vcc dq10 h2 h2 h3 h3 f2 f2 f3 f3 e2 e3 a6 a3 a5 a2 a4 a1 vss a0 l4 l4 l5 l5 l6 l6 l7 l7 l8 l8 l2 l 2 l3 l3 m2 m3 r-vcc dq8 a27 a26 vss dq12 f-wp# dq14 dq5 a25 dq11 dq2 m4 m6 m8 m9 f-vccq r-vccq f4-ce# f-vcc vss dnu dnu dnu legend: code flash only dnu (do not use) psram only flash/xram shared k6 d4 b2 dnu dnu a1 dnu dnu b9 dnu dnu b10 dnu dnu dnu dnu dnu dnu dnu p2 dnu e4 e6 mirrorbit data only xram shared flash/data shared see table m7 d2 d5 f5 nc wp#/ acc ry/ by# f-wp# acc f-rdy/ r-wait# ball 3.0v vcc 1.8v vcc table d-dm1/ d11, d# fasl standard mcp packages 7.0 x 9.0mm 8.0 x 11.6mm 9.0 x 12.0mm 11.0 x 13.0mm n9 p9 p10 n10 n1 n2 p1 m5 k2 l2 j2 k5 g2 g2 g3 g3 g4 g4 g6 g6 g7 g7 g8 g8 g9 g9 l9 a9 a10 b1 a2 dnu 96-ball fine-pitch ball grid array (top view, balls facing down)
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 9 input/output descriptions a23-a0 = address inputs dq15-dq0 = data input/output oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v ss = ground nc = no connect; not connected internally rdy = ready output. indicates the status of the burst read. the wait# pin of the psram is tied to rdy. clk = clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode avd# = address valid input. indicates to device that the valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs f-rst# = hardware reset input. low = device resets and returns to reading array data f-wp# = hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc = accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce1# = chip-enable input for psram. f1-ce# = chip-enable input for flash 1. asynchronous relative to clk for burst mode. f2-ce# = chip-enable input for flash 2. asynchronous relative to clk for burst mode. this applies to the 512mb mcp only. r-mrs = mode register select for type 4. f-vcc = flash 1.8 volt-only single power supply. r-vcc = psram power supply. r-ub# = upper byte control (psram). r-lb# = lower byte control (psram). dnu = do not use.
10 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_ut november 8, 2004 ordering information the order number (valid combination) is formed by the following: s71ws 256 n d 0 ba w a 3 0 packing type 0=tray 1=tube 2 = 7? tape and reel 3 = 13? tape and reel supplier, dyb, speed combination 3 = ram type 4, 0, 54mhz 7 = ram type 4, 1, 54mhz package modifier a = 1.2mm, 8 x 11.6, 84-ball fbga y = 1.4mm, 9 x 12, 84-ball fbga e = 1.2mm, 9 x 12, 84-ball fbga temperature range w=wireless (-25 c to +85 c) i = industrial (?40 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package chip contents?2 no second content chip contents?1 c = 64mb d = 128mb process technology n = 110nm mirrorbit? technology flash density 512 = 512mb (2x256mb) 256 = 256mb device family s71ws= multi-chip product 1.8 volt-only simultaneous read/write burst mode flash memory + xram
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 11 valid combinations 256mb - ws256n flash + 128 psram 2x256mb?ws256n flash + 128mb psram order number package marking temperature range c burst speed dyb power- up sta te material set supplier s71ws256nd0bawe3 71ws256nd0bawe3 -25 to +85c 54mhz 0(protected) pb-free compliant 1.8v ram typ e 4 s71ws256nd0bawe7 71ws256nd0bawe7 1(unprotected [default state]) s71ws256nd0baie3 71ws256nd0baie3 -40 to +85c 0(sectors protected) 1.8v ram typ e 4 s71ws256nd0baie7 71ws256nd0baie7 1(unprotected [default state]) s71ws256nd0bfwe3 71ws256nd0bfwe3 -25 to +85c 0(protected) pb-free 1.8v ram typ e 4 s71ws256nd0bfwe7 71ws256nd0bfwe7 1(unprotected [default state]) s71ws256nd0bfie3 71ws256nd0bfie3 -40 to +85c 0(protected) 1.8v ram typ e 4 s71ws256nd0bfie7 71ws256nd0bfie7 1(unprotected [default state]) order number package marking te m p e r a t u r e range c burst speed dyb power-up st ate material set supplier s71ws512nd0bawe3 71ws512nd0bawe3 -25 to +85c 54mhz 0(protected) pb-free compliant 1.8v ram type 4 s71ws512nd0bawe7 71ws512nd0bawe7 1(unprotected [default state]) s71ws512nd0baie3 71ws512nd0baie3 -40 to +85c 0(protected) 1.8v ram type 4 s71ws512nd0baie7 71ws512nd0baie7 1(unprotected [default state]) s71ws512nd0bfwe3 71ws512nd0bfwe3 -25 to +85c 0(protected) pb-free 1.8v ram type 4 s71ws512nd0bfwe7 71ws512nd0bfwe7 1(unprotected [default state]) s71ws512nd0bfie3 71ws512nd0bfie3 -40 to +85c 0(protected) 1.8v ram type 4 s71ws512nd0bfie7 71ws512nd0bfie7 0(protected)
12 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_ut november 8, 2004 physical dimensions fea084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 mm mcp compatible package 3423 \ 16-038.21a package fea 084 jedec n/a d x e 12.00 mm x 9.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.11 --- 1.26 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 0.15 c a b m c m 0.08
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 13 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 mm mcp compatible package 3426\ 16-038.22 package tsd 084 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.94 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 m c mc ab 0.08 pin a1 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd
14 s71ws512nx0/s71ws256nx0 s71ws512/256nx0_ut november 8, 2004 tla084?84-ball fine-pitch ball grid array (fbga) 11.6x8.0x1.2 mm mcp compatible package note: bsc is an ansi standard for basic space centering 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
publication number s29wsxxxn_m0 revision f amendment 0 issue date november 4, 2004 general description the spansion s29ws256/128/064n are mirrorbit tm flash products fabricated on 110 nm process technology. these burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. they operate up to 80 mhz and use a single v cc of 1.7?1.95 volts that makes them ideal for today?s demanding wireless applications requiring higher density, better performance and lowered power consumption. distinctive characteristics ? single 1.8 v read/program/erase (1.70?1.95 v) ? 110 nm mirrorbit? technology ? simultaneous read/write operation with zero latency ? 32-word write buffer ? sixteen-bank architecture consisting of 16/8/4 mbit for ws256n/128n/064n, respectively ? four 16 kword sectors at both top and bottom of memory array ? 254/126/62 64 kword sectors (ws256n/128n/ 064n) ? programmable burst read modes ? linear for 32, 16 or 8 words linear read with or without wrap-around ? continuous sequential read mode ? secsi? (secured silicon) sector region consisting of 128 words each for factory and customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec standards ? hardware (wp#) protection of top and bottom sectors ? dual boot sector configuration (top and bottom) ? offered packages ? ws064n: 80-ball fbga (7 mm x 9 mm) ? ws256n/128n: 84-ball fbga (8 mm x 11.6 mm) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst co ntrol register settings ? acc input pin to reduce factory programming time ? support for common flash interface (cfi) ? industrial temperature range (contact factory) performance characteristics s29wsxxxn mirrorbit? flash family s29ws256n, s29ws128n, s29ws064n 256/128/64 megabit (16/8/4 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory data sheet preliminary read access times speed option (mhz) 806654 max. synch. latency, ns (t iacc ) 696969 max. synch. burst access, ns (t bacc ) 9 11.2 13.5 max. asynch. access time, ns (t acc ) 707070 max ce# access time, ns (t ce ) 707070 max oe# access time, ns (t oe ) 11.2 11.2 13.5 current consumption (typical values) continuous burst read @ 66 mhz 35 ma simultaneous operation (asynchronous) 50 ma program (asynchronous) 19 ma erase (asynchronous) 19 ma standby mode (asynchronous) 20 a typical program & erase times single word programming 40 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v acc ) per word 6 s sector erase (16 kword sector) 150 ms sector erase (64 kword sector) 600 ms
16 s29wsxxxn mirrorbit? flash family s29wsxxxn_m0f0 november 4, 2004 preliminary 1 input/output descriptions & logic symbol table identifies the input and output package connections provided on the device. table 1.1. input/output descriptions symbol type description a23?a0 input address lines for ws256n (a22-a0 for ws128 and a21-a0 for ws064n). dq15?dq0 i/o data input/output. ce# input chip enable. asynchronous relative to clk. oe# input output enable. asynchronous relative to clk. we# input write enable. v cc supply device power supply. v io input versatileio input. should be tied to v cc . v ss i/o ground. nc no connect not connected internally. rdy output ready. indicates when valid burst data is ready to be read. clk input clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode. avd# input address valid. indicates to device that the valid address is present on the address inputs. when low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. when high, device ignores address inputs. reset# input hardware reset. low = device resets and returns to reading array data. wp# input write protect. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. acc input acceleration input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. rfu reserved reserved for future use (see mcp look-ahead pinout for use with mcp).
november 4, 2004 s29wsxxxn_m0_f0 s29wsxxxn mirrorbit? flash family 17 preliminary 2 block diagram figure 2.1. s29wsxxxn block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a max ?a0* rdy buffer rdy burst state control burst address counter avd# clk * ws256n: a23-a0 ws128n: a22-a0 ws064n: a21-a0
november 4, 2004 s29wsxxxn_m0_f0 18 preliminary 3 additional resources visit www.amd.com and www.fujitsu.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? understanding burst mode flash memory devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad technical support contact your local sales office or contact spansion llc directly for additional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujitsu.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion llc locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
19 s29wsxxxn_m0_f0 november 4, 2004 preliminary 4 product overview the s29wsxxxn family consists of 256, 128 and 64mbit, 1.8 volts-only, simultaneous read/ write burst mode flash device optimized for today?s wireless designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 16, 8 or 4 mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. these prod- ucts also offer single word programming or a 32-word buffer for programming with program/ erase and suspend functionality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon (secsi?) area for storing customer and factory secured in - formation. the secsi sector is one time programmable and protectable (ottp). 4.1 memory map the s29ws256/128/064n mbit devices consist of 16 banks organized as shown in tables 4.1? 4.3. note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not explicitly listed (such as sa005?sa017 ) have sector starting and ending addresses that form the sam e pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 4.1. s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 2 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 15 128 sa004 to sa018 010000h?01ffffh to 0f0000h?0fffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 2 mb 16 128 1 sa019 to sa034 100000h?10ffffh to 1f0000h?1fffffh 2 mb 16 128 2 sa035 to sa050 200000h?20ffffh to 2f0000h?2fffffh 2 mb 16 128 3 sa051 to sa066 300000h?30ffffh to 3f0000h?3fffffh 2 mb 16 128 4 sa067 to sa082 400000h?40ffffh to 4f0000h?4fffffh 2 mb 16 128 5 sa083 to sa098 500000h?50ffffh to 5f0000h?5fffffh 2 mb 16 128 6 sa099 to sa114 600000h?60ffffh to 6f0000h?6fffffh 2 mb 16 128 7 sa115 to sa130 700000h?70ffffh to 7f0000h?7fffffh 2 mb 16 128 8 sa131 to sa146 800000h?80ffffh to 8f0000h?8fffffh 2 mb 16 128 9 sa147 to sa162 900000h?90ffffh to 9f0000h?9fffffh 2 mb 16 128 10 sa163 to sa178 a00000h?a0ffffh to af0000h?afffffh 2 mb 16 128 11 sa179 to sa194 b00000h?b0ffffh to bf0000h?bfffffh 2 mb 16 128 12 sa195 to sa210 c00000h?c0ffffh to cf0000h?cfffffh 2 mb 16 128 13 sa211 to sa226 d00000h?d0ffffh to df0000h?dfffffh 2 mb 16 128 14 sa227 to sa242 e00000h?e0ffffh to ef0000h?efffffh 2 mb 15 128 15 sa243 to sa257 f00000h?f0ffffh to fe0000h?feffffh 4 32 sa258 ff0000h?ff3fffh contains four smaller sectors at top of addressable memory. sa259 ff4000h?ff7fffh sa260 ff8000h?ffbfffh sa261 ffc000h?ffffffh
november 4, 2004 s29wsxxxn_m0_f0 20 preliminary note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not explicitly listed (such as sa005?sa009 ) have sector starting and ending addresses that form the sam e pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 4.2. s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 1 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. 32 sa001 004000h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 7 128 sa004 to sa010 010000h?01ffffh to 070000h?07ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 1 mb 8 128 1 sa011 to sa018 080000h?08ffffh to 0f0000h?0fffffh 1 mb 8 128 2 sa019 to sa026 100000h?10ffffh to 170000h?17ffffh 1 mb 8 128 3 sa027 to sa034 180000h?18ffffh to 1f0000h?1fffffh 1 mb 8 128 4 sa035 to sa042 200000h?20ffffh to 270000h?27ffffh 1 mb 8 128 5 sa043 to sa050 280000h?28ffffh to 2f0000h?2fffffh 1 mb 8 128 6 sa051 to sa058 300000h?30ffffh to 370000h?37ffffh 1 mb 8 128 7 sa059 to sa066 380000h?38ffffh to 3f0000h?3fffffh 1 mb 8 128 8 sa067 to sa074 400000h?40ffffh to 470000h?47ffffh 1 mb 8 128 9 sa075 to sa082 480000h?48ffffh to 4f0000h?4fffffh 1 mb 8 128 10 sa083 to sa090 500000h?50ffffh to 570000h?57ffffh 1 mb 8 128 11 sa091 to sa098 580000h?58ffffh to 5f0000h?5fffffh 1 mb 8 128 12 sa099 to sa106 600000h?60ffffh to 670000h?67ffffh 1 mb 8 128 13 sa107 to sa114 680000h?68ffffh to 6f0000h?6fffffh 1 mb 8 128 14 sa115 to sa122 700000h?70ffffh to 770000h?77ffffh 1 mb 7 128 15 sa123 to sa129 780000h?78ffffh to 7e0000h?7effffh 4 32 sa130 7f0000h?7f3fffh contains four smaller sectors at top of addressable memory. 32 sa131 7f4000h?7f7fffh 32 sa132 7f8000h?7fbfffh 32 sa133 7fc000h?7fffffh
21 s29wsxxxn_m0_f0 november 4, 2004 preliminary note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not explicitly listed (such as sa008?sa009 ) have sector starting and ending addresses that form the sam e pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 4.3. s29ws064n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 0.5 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 3 128 sa004 010000h?01ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) sa005 020000h?02ffffh sa006 030000h?03ffffh 0.5 mb 4 128 1 sa007?sa010 040000h?04ffffh to 070000h?07ffffh 0.5 mb 4 128 2 sa011?sa014 080000h?08ffffh to 0b0000h?0bffffh 0.5 mb 4 128 3 sa015?sa018 0c0000h?0cffffh to 0f0000h?0fffffh 0.5 mb 4 128 4 sa019?sa022 100000h?10ffffh to 130000h?13ffffh 0.5 mb 4 128 5 sa023?sa026 140000h?14ffffh to 170000h?17ffffh 0.5 mb 4 128 6 sa027?sa030 180000h?18ffffh to 1b0000h?1bffffh 0.5 mb 4 128 7 sa031?sa034 1c0000h?1cffffh to 1f0000h?1fffffh 0.5 mb 4 128 8 sa035?sa038 200000h?20ffffh to 230000h?23ffffh 0.5 mb 4 128 9 sa039?sa042 240000h?24ffffh to 270000h?27ffffh 0.5 mb 4 128 10 sa043?sa046 280000h?28ffffh to 2b0000h?2bffffh 0.5 mb 4 128 11 sa047?sa050 2c0000h?2cffffh to 2f0000h?2fffffh 0.5 mb 4 128 12 sa051?sa054 300000h?30ffffh to 330000h?33ffffh 0.5 mb 4 128 13 sa055?sa058 340000h?34ffffh to 370000h?37ffffh 0.5 mb 4 128 14 sa059?sa062 380000h?38ffffh to 3b0000h?3bffffh 0.5 mb 3 128 15 sa063 3c0000h?3cffffh sa064 3d0000h?3dffffh sa065 3e0000h?3effffh 4 32 sa066 3f0000h?3f3fffh contains four smaller sectors at top of addressable memory. sa067 3f4000h?3f7fffh sa068 3f8000h?3fbfffh sa069 3fc000h?3fffffh
november 4, 2004 s29wsxxxn_m0_f0 22 preliminary 5 device operations this section describes the read, program, erase, simultaneous read/write operations, hand- shaking, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see tables 10.1 and 10.2 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. writing incorrect address and data values or writing them in an improper sequen ce may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 5.1 device operation table the device must be setup appropriately for each operation. ta b l e 5 . 4 describes the required state of each control pin for any particular operation. ta b l e 5 . 4 . device operations legend: l = logic 0, h = logic 1, x = don?t care, i/o = input/output. 5.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. the device defaults to reading array data asynchronously after device power-up or hardware reset. to read data from the memory array, the system must first assert a valid address on a max ?a0, while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address and data will appear on dq15?dq0 after address access time (t acc ), which is equal to the delay from stable addresses to valid output data. the chip enable operation ce# oe# we# addresses dq15?0 reset# clk avd# asynchronous read - addresses latched l l h addr in data out h x asynchronous read - addresses steady state l l h addr in data out h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations (synchronous) load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus l l h x burst data out h h terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle l x h addr in i/o h
23 s29wsxxxn_m0_f0 november 4, 2004 preliminary access time (t ce ) is the delay from the stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. 5.3 synchronous (burst) read mode & configuration register when a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. after an initial access time re- quired for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. the device offers both continuous and linear methods of burst read operation, which are dis- cussed in subsections 5.3.1 and 5.3.2, and 5.3.3. since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. other configuration regis- ter settings include the number of wait states to insert before the initial word (t iacc ) of each burst access, the burst mode in which to operate, and when rdy will indicate data is ready to be read. prior to entering the burst mode, the system should first determine the configu- ration register settings (and read the current register settings if desired via the read configuration register command sequence), and then write the configuration register com- mand sequence. see section 5.3.4 , configuration register , and table 10.1 , memory array commands for further details. figure 5.1. synchronous/asynchronous state diagram the device outputs the initial word subject to the following operational conditions: ? t iacc specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. ? configuration register setting cr13?cr11: th e total number of clock cycles (wait states) that occur before valid data appears on the device outputs. the effect is that t iacc is lengthened. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1)
november 4, 2004 s29wsxxxn_m0_f0 24 preliminary the device outputs subsequent words t bacc after the active edge of each successive clock cy- cle, which also increments the internal address counter. the device outputs burst data at this rate subject to the following operational conditions: ? starting address: whether the address is divisible by four (where a[1:0] is 00). a divisi - ble-by-four address incurs the least number of additional wait states that occur after the initial word. the number of additional wait states required increases for burst operations in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where a[1:0] is 01, 10, or 11). ? boundary crossing: a physical aspect of the device that exists every 128 words, starting at address 00007fh. higher operational speeds require one additional wait state. refer to ta b l e s 5.10 ? 5.13 for details. figure 9.20 shows the effects of boundary crossings at higher frequencies. ? clock frequency: the speed at which the device is expected to burst data. higher speeds require additional wait states after the initial word for proper operation. ta b l e s 5.7 ? 5.13 show the effects of frequency on burst operation. in all cases, with or without latency, the rdy output indicates when the next data is available to be read. ta b l e 5 . 5 shows the latency that occurs in the s29ws256n device when (x indicates the rec- ommended number of wait states for various operating frequencies, as shown in table 5.15 , configuration register bits cr13-cr11). tab le s 5.7?5.9 show the effects of various combinations of the starting address, operating frequency, and wait state setting (configuration register bits cr13?cr11) for the s29ws128n and s29ws064n devices. tables 5.10?5.13 includes the wait state that occurs when crossing the internal boundary. table 5.5. address latency for x wait states ( 80 mhz, ws256n only) ta b l e 5 . 6 . address latency for 6 wait states ( 80 mhz) ta b l e 5 . 7 . address latency for 5 wait states ( 68 mhz) word wait states cycle 0 x ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 x ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 x ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 x ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 6 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 6 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 6 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 6 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5 ws d1 d2 d3 d4 d5 d6 d7 d8 d9 2 5 ws d2 d3 1 ws d4 d5 d6 d7 d8 d9 3 5 ws d3 1 ws 1 ws d4 d5 d6 d7 d8 d9
25 s29wsxxxn_m0_f0 november 4, 2004 preliminary ta b l e 5 . 8 . address latency for 4 wait states ( 54 mhz) ta b l e 5 . 9 . address latency for 3 wait states ( 40 mhz) ta b l e 5 . 1 0 . address/boundary crossing latency for 6 wait states ( 80 mhz) ta b l e 5 . 1 1 . address/boundary crossing latency for 5 wait states ( 68 mhz) ta b l e 5 . 1 2 . address/boundary crossing latency for 4 wait states ( 54 mhz) ta b l e 5 . 1 3 . address/boundary crossing latency for 3 wait states ( 40 mhz) word wait states cycle 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 4 ws d1 d2 d3 d4 d5 d6 d7 d8 d9 2 4 ws d2 d3 d4 d5 d6 d7 d8 d9 d10 3 4 ws d3 1 ws d4 d5 d6 d7 d8 d9 d10 word wait states cycle 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 3 ws d1 d2 d3 d4 d5 d6 d7 d8 d9 2 3 ws d2 d3 d4 d5 d6 d7 d8 d9 d10 3 3 ws d3 d4 d5 d6 d7 d8 d9 d10 d11 word wait states cycle 0 6 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 6 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 6 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 6 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7 word wait states cycle 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 word wait states cycle 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 4 ws d1 d2 d3 d4 d5 d6 d7 d8 d9 2 4 ws d2 d3 1 ws d4 d5 d6 d7 d8 d9 3 4 ws d3 1 ws 1 ws d4 d5 d6 d7 d8 d9 word wait states cycle 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 3 ws d1 d2 d3 d4 d5 d6 d7 d8 d9 2 3 ws d2 d3 d4 d5 d6 d7 d8 d9 d10 3 3 ws d3 1 ws d4 d5 d6 d7 d8 d9 d10
november 4, 2004 s29wsxxxn_m0_f0 26 preliminary figure 5.2. synchronous read 5.3.1 continuous burst read mode in the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addres- sable memory location. the burst read mode will continue until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. if the address being read crosses a 128-word line boundary and the subsequent word line is not programming or erasing, additional latency cycles are required as shown in tables 5.10? 5.13 . if the address crosses a bank boundary while the subsequent bank is programming or eras- ing, the device will provide read status information and the clock will be ignored. upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and avd# pulse. write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait t iacc + programmable wait state setting wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 cr13-cr11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles see tables 5.6?5.13 to determine total number of clocks required for x.
27 s29wsxxxn_m0_f0 november 4, 2004 preliminary 5.3.2 8-, 16-, 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 5.14 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3fh, and the burst sequence would be 3c-3d-3e-3f-38-39-3a-3bh. thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the addres s group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, then wrap back to the first address in the se- lected address group. note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). ta b l e 5 . 1 4 . burst address groups 5.3.3 8-, 16-, 32-word linear burst without wrap around if wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32- word burst will execute up to the maximum memory address of the selected number of words. the burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. for example, if the starting address in the 8- word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence wo uld be 3c-3d-3e-3f-40-41-42-43h if wrap around is not enabled. the next address to be read will require a new address and avd# pulse. note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words. 5.3.4 configuration register the configuration register sets various operat ional features, most of which are associated with burst mode. upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. the host system should determine the proper settings for the entire configuration register, and then execute the set configuration register command sequence, before attempting burst operations. the configuration register is not reset after deasserting ce#. the configuration register can also be read using a command sequence (see ta b l e 1 0 . 1 ). the following list describes the register settings. mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
november 4, 2004 s29wsxxxn_m0_f0 28 preliminary ta b l e 5 . 1 5 . configuration register reading the configuration table. the configuration register can be read with a four-cycle command sequence. see table 10.1 for sequence details. once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. 5.4 autoselect the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on dq15-dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming al- gorithm. the autoselect codes can also be accessed in-system. when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 5.17 to 5.16 ). the remaining address bits are don't care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15-dq0. the autoselect codes can also be accessed in-system through the com- mand register. note that if a bank address (ba) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. cr bit function settings (binary) cr15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous read mode (default) enabled cr14 boundary crossing 0 = no extra boundary crossing latency 1 = with extra boundary crossing latency (default) must be set to ?1? at higher operating frequencies. see tables 5.10 ? 5.13 . cr13 cr12 cr11 programmable wait state 000 = data valid on 2nd active clk edge after addresses latched 001 = data valid on 3rd active clk edge after addresses latched 010 = data valid on 4th active clk edge after addresses latched (recommended for 54 mhz) 011 = data valid on 5th active clk edge after addresses latched (recommended for 66 mhz) 100 = data valid on 6th active clk edge after addresses latched (recommended for 80 mhz) 101 = data valid on 7th active clk edge after addresses latched (default) 110 = reserved 111 = reserved inserts wait states before initial data is available. setting greater number of wait states before initial data reduces latency after initial data. see tables 5.6 ? 5.13 . cr10 rdy polarity 0 = rdy signal active low 1 = rdy signal active high (default) cr9 reserved 1 = default cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) when cr13-cr11 are set to 000, rdy will be active with data regardless of cr8 setting. cr7 reserved 1 = default cr6 reserved 1 = default cr5 reserved 0 = default cr4 reserved 0 = default cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 cr1 cr0 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) note: configuration register will be in the defaul t state upon power-up or hardware reset.
29 s29wsxxxn_m0_f0 november 4, 2004 preliminary ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing in the other bank. autoselect does not support simultaneous operations or burst mode. ? the system must write the reset command to return to the read mode (or erase-suspend- read mode if the bank was previously in erase suspend). see ta b l e 1 0 . 1 for command sequence details. ta b l e 5 . 1 6 . autoselect addresses description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2230 (ws256n) 2231 (ws128n) 2232 (ws064n) device id, word 3 (ba) + 0fh 2200 indicator bits (see note) (ba) + 03h dq15 - dq8 = reserved dq7 (factory lock bit): 1 = locked, 0 = not locked dq6 (customer lock bit): 1 = locked, 0 = not locked dq5 (handshake bit): 1 = reserved, 0 = standard handshake dq4, dq3 (wp# protection boot code): 00 = wp# protects both top boot and bottom boot sectors. 01, 10, 11 = reserved dq2 = reserved dq1 (dyb power up state [lock register dq4]): 1 = unlocked (user option), 0 = locked (default) dq0 (ppb eraseability [lock register dq3]): 1 = erase allowed, 0 = erase disabled sector block lock/ unlock (sa) + 02h 0001h = locked, 0000h = unlocked note: for ws128n and ws064, dq1 and dq0 will be reserved. software functions and sample code table 5.17. autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write baxaaah bax555h 0x00aah unlock cycle 2 write bax555h bax2aah 0x0055h autoselect command write baxaaah bax555h 0x0090h
november 4, 2004 s29wsxxxn_m0_f0 30 preliminary notes: 1. any offset within the device will work. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manu- facturer id. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software develop- ment guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ table 5.18. autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxh base + xxxh 0x00f0h
31 s29wsxxxn_m0_f0 november 4, 2004 preliminary 5.5 program/erase operations these devices are capable of several modes of programming and or erase operations which are described in details during the following sections. however, prior to any programming and or erase operation, devices must be setup appropriately as outlined in ta b l e 5 . 4 . during a synchronous write operation, to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and da ta. addresses are latched on the last fall- ing edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is complete, the device then returns to the read mode. ? the system can determine the status of the program operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. ? a ?0? cannot be programmed back to a ?1.? at tempting to do so will cause the device to set dq5 = 1 (halting any further operation and requiring a reset command). a succeeding read will show that the data is still ?0.? ? only erase operations can convert a ?0? to a ?1.? ? any commands written to the device during the embedded program algorithm are ig - nored except the program suspend command. ? secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. ? a hardware reset immediately terminates the program operation and the program com - mand sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word programming operation. ? programming to the same word address multiple times without intervening erases is lim - ited. for such application requirements, please contact your local spansion representa - tive. 5.5.1. single word programming single word programming mode is the simplest method of programming. in this mode, four flash command write cycles are used to program an individual flash address. the data for this programming operation could be 8-, 16- or 32-bits wide. while this method is supported by all spansion devices, in general it is not recommended for devices that support write buffer programming. see ta b l e 1 0 . 1 for the required bus cycles and figure 5.19 for the flowchart. when the embedded program algorithm is comp lete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the pro- gram operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. ? during programming, any command (except the suspend program command) is ignored. ? the secsi sector, autoselect, and cfi functions are unavailable when a program opera - tion is in progress.
november 4, 2004 s29wsxxxn_m0_f0 32 preliminary ? a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming to the same address multiple ti mes continuously (for example, ?walking? a bit within a word) for an extended period is not recommended. for more information, contact your local sales office. figure 5.19. single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
33 s29wsxxxn_m0_f0 november 4, 2004 preliminary note: base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 5.5.2 write buffer programming write buffer programming allows the system to write a maximum of 32 words in one pro- gramming operation. this results in a faster effective word programming time than the standard ?word? programming algorithms. the write buffer programming command se- quence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which program- ming will occur. at this point, the system writes the number of ?word locations minus 1? that will be loaded into the page buffer at the sector address in which programming will occur. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the ?program buffer to flash? confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. (number loaded = the number of locations to program minus 1. for example, if the system will pro- gram 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the ?write-buffer-page? address. all subsequent address/data pairs must fall within the elected-write-buffer-page. the ?write-buffer-page? is selected by using the addresses a max - a5. the ?write-buffer-page? addresses must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple ?write-buffer-pages.? this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the se- lected ?write-buffer-page?, the operation will abort.) after writing the starting address/data pair, the system then writes the remaining address/ data pairs into the write buffer. note that if a write buffer address location is loaded multiple times, the ?address/data pair? counter will be decremented for every data load operation. also, the last data loaded at a lo- cation before the ?program buffer to flash? confirm command will be programmed into the software functions and sample code ta b l e 5 . 2 0 . s i n g l e wo r d p r o g r a m (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word
november 4, 2004 s29wsxxxn_m0_f0 34 preliminary device. it is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. once the specified number of write buffer locations have been loaded, the system must then write the ?program buffer to flash? command at the sector address. any other address/data write combinations will abort the write buffer pro- gramming operation. the device will then ?go busy.? the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an address in memory because the system can load the last address loca- tion, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to deter- mine the device status during write buffer programming. the write-buffer ?embedded? programming operation can be suspended using the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device will return to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the ?number of locations to program? step. ? write to an address in a sector different than the one specified during the write-buffer- load command. ? write an address/data pair to a different write-buffer-page than the one selected by the ?starting address? during the ?write buffer data loading? stage of the operation. ? write data other than the ?confirm command? after the specified number of ?data load? cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last address location loaded?), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming oper- ation was aborted. a ?write-to-buffer-abort reset? command sequence is required when using the write buffer programming features in unlock bypass mode. note that the secsi tm sector, autoselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. however, programming the same word address multiple times without inte rvening erases requires a modified program- ming method. please contact your local spansion tm representative for details. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. write buffer programming is approximately eight times faster than pro- gramming one word at a time.
35 s29wsxxxn_m0_f0 november 4, 2004 preliminary notes: 1. base = base address. 2. last = last cycle of write buffer prog ram operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible. the following is a c source code example of using the write buffer program function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 5.21. write buffer program (lld functions used = lld_writetobuffercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
november 4, 2004 s29wsxxxn_m0_f0 36 preliminary figure 5.22. write buffer programming operation 5.5.3 sector erase the sector erase function erases one or more sectors in the memory array. (see table 10.1 , memory array commands ; and figure 5.24 , sector erase operation .) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automati- cally programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa 29h wait 4 s perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
37 s29wsxxxn_m0_f0 november 4, 2004 preliminary sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see the ?dq3: sector erase timer? sec- tion.) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to ?write operation status? for information on these status bits. once the sector erase operation has begun, on ly the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 5.24 illustrates the algorithm for the erase operation. refer to the ?erase/program op- erations? section for parameters and timing diagrams.
november 4, 2004 s29wsxxxn_m0_f0 38 preliminary the following is a c source code example of using the sector erase function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ software functions and sample code table 5.23. sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea .
39 s29wsxxxn_m0_f0 november 4, 2004 preliminary figure 5.24. sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? each additional cycle must be written within t sea timeout timeout resets after each additional cycle is written the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands no limit on number of sectors commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data notes: 1. see table 10.1 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. (see figure 5.33)
november 4, 2004 s29wsxxxn_m0_f0 40 preliminary 5.5.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 10.1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automati cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the ?command definition? section in the appendix shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to ?write operation status? for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the following is a c source code example of using the chip erase function. refer to the span- sion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ 5.5.5 erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank ad- dress is required when writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase com- mand sequence. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. how- software functions and sample code table 5.25. chip erase (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h
41 s29wsxxxn_m0_f0 november 4, 2004 preliminary ever, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to ta b l e 5 . 3 5 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-sus- pend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system can also issue the autoselect command se- quence. refer to the ?write buffer programming operation? section and the ?autoselect command sequence? section for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. fur- ther writes of the resume command are igno red. another erase suspend command can be written after the chip has resumed erasing. the following is a c source code example of using the erase suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the erase resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 5.5.6 program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming operation or a ?write to buffer? programming operation so that data can read from any non- suspended sector. when the program suspend command is written during a programming process, the device halts the programming operation within t psl (program suspend latency) software functions and sample code table 5.26. erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h table 5.27. erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
november 4, 2004 s29wsxxxn_m0_f0 42 preliminary and updates the status bits. addresses are ?d on't-cares? when writing the program suspend command. after the programming operation has been suspen ded, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sec- tor area, then user must use the proper comma nd sequences to enter and exit this region. the system may also write the autoselect comm and sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. after the program resume command is written, the device reverts to programming. the sys- tem can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system must write the program resume command (address bits are ?don't care?) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. the following is a c source code example of using the program suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the program resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 5.5.7 accelerated program/chip erase accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the acc function. this method is faster than the stan- dard chip program and erase command sequences. software functions and sample code table 5.28. program suspend (lld function = lld_programsuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h table 5.29. program resume (lld function = lld_programresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
43 s29wsxxxn_m0_f0 november 4, 2004 preliminary the accelerated chip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program and erase should be performed at room temperature (25 c 10 c). if the system asserts v hh on this input, the device automatically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. the system can then use the write buffer load command se- quence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embed- ded program or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising acc to v hh . ? the acc pin must not be at v hh for operations other than accelerated programming and accelerated chip erase, or device damage may result. ? the acc pin must not be left floating or unco nnected; inconsistent behavior of the device may result. ? t acc locks all sector if set to v il ; t acc should be set to v ih for all other conditions. 5.5.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the device enters the unlock bypass mode, only two write cycles are required to program data, instead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program com- mand sequence, resulting in faster total programming time. the ?command definition summary? section shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two- cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the following are c source code examples of using the unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ software functions and sample code table 5.30. unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h
november 4, 2004 s29wsxxxn_m0_f0 44 preliminary /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 5.5.9 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the com- mand sequence. note that the data# polling is valid only for the last word being programmed in the write-buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase sus- pend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status in- formation on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the em- bedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the un- protected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the table 5.31. unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data table 5.32. unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h
45 s29wsxxxn_m0_f0 november 4, 2004 preliminary system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6- dq0 may be still invalid. valid data on dq7-d00 will appear on successive read cycles. see the following for more information: ta b l e 5 . 3 5 , write operation status , shows the out- puts for data# polling on dq7. figure 5.33 , write operation status flowchart , shows the data# polling algorithm; and figure 9.16 , data# polling timings (during embedded algorithm) , shows the data# polling timing diagram.
november 4, 2004 s29wsxxxn_m0_f0 46 preliminary figure 5.33. write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
47 s29wsxxxn_m0_f0 november 4, 2004 preliminary dq6: toggle bit i . toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase opera- tion), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any ad- dress cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to read- ing array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase al- gorithm is in progress), dq6 toggles. when th e device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are eras- ing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately t pap after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the em- bedded program algorithm is complete. see the following for additional information: figure 5.33 , write operation status flowchart ; figure 9.17 , toggle bit timings (during embedded algorithm) , and tables 5.34 and 5.35. toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii . the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-su spended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 5 . 3 4 to compare outputs for dq2 and dq6. see the following for additional in- formation: figure 5.33, the ?dq6: toggle bit i? section, and figures 9.16?9.19.
november 4, 2004 s29wsxxxn_m0_f0 48 preliminary ta b l e 5 . 3 4 . dq6 and dq2 indications reading toggle bits dq6/dq2. whenever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may con- tinue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 5.33 for more details. dq5: exceeded timing limits. dq5 indicates whether the program or erase time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this con- dition, the device halts the operation, and wh en the timing limit has been exceeded, dq5 produces a ?1.?under both these conditions, the system must write the reset command to re- turn to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator. after writing a sector erase command se- quence, the system may read dq3 to determin e whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are se- lected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
49 s29wsxxxn_m0_f0 november 4, 2004 preliminary after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further com- mands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 5 . 3 5 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort. dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write to buffer abort reset command sequence to return the device to reading array data. see write buffer pro- gramming operation for more details. ta b l e 5 . 3 5 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer pro gramming indicates the data-bar for dq7 data for the last loaded write-buffer address location . status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (note 5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1
november 4, 2004 s29wsxxxn_m0_f0 50 preliminary 5.6 simultaneous read/write the simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 9.23 , back-to-back read/write cycle timings , shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics (cmos compatible) table for read-while-program and read-while-erase current specification. 5.7 writing commands/command sequences when the device is configured for asynchronous read, only asynchronous write operations are allowed, and clk is ignored. when in the synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. clk and avd# in- duced address latches are supported in the synchronous programming mode. during a synchronous write operation, to write a command or command sequence (which includes pro- gramming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector, multiple sectors, or the entire device. tables 4.1?4.3 indicate the address space that each sector occupies. the device address space is divided into sixteen banks: banks 1 through 14 contain only 64 kword sectors, while banks 0 and 15 contain both 16 kword boot sectors in addition to 64 kword sectors. a ?bank address? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in ?dc characteristics? represents the active current specification for the write mode. ?ac characteristics-synchronous? and ?ac characteristics-asynchronous? con- tain timing specification tables and timing diagrams for write operations. 5.8 handshaking the handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the rdy (ready) pin, which is a dedicated output and controlled by ce#. when the device is configured to operate in synchronous mode, and oe# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the rdy pin (depending on the setting for bit 10 in the configuration register). it is recommended that the host system set cr13?cr11 in the configuration register to the appropriate number of wait states to ensure optimal burst mode operation (see table 5.15 , configuration register ). bit 8 in the configuration register allows the host to specify whether rdy is active at the same time that data is ready, or one cycle before data is ready.
51 s29wsxxxn_m0_f0 november 4, 2004 preliminary 5.9 hardware reset the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the inter- nal state machine to reading array data. to ensure data integrity the operation that was interrupted should be reinitiated once the de- vice is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current will be greater. reset# may be tied to the system reset circuitry which enables the system to read the boot- up firmware from the flash memory upon a system reset. see figures 9.5 and 9.12 for timing diagrams. 5.10 software reset software reset is part of the command set (see ta b l e 1 0 . 1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status op eration that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. after any aborted operations note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to the read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is complete ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). this resets the bank to which the system was writing to the read mode. software functions and sample code table 5.36. reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
november 4, 2004 s29wsxxxn_m0_f0 52 preliminary ? if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer programming operation, the system must write the "write to buffer abort reset" command sequence to reset the device to reading array data. the standard reset command will not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details].
53 s29wsxxxn_m0_f0 november 4, 2004 preliminary 6 advanced sector protection/unprotection the advanced sector protection/unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hard- ware methods, which are independent of each other. this section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 6.1. figure 6.1. advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (ppb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector.
november 4, 2004 s29wsxxxn_m0_f0 54 preliminary 6.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the dyb ordering option. the device programmer or host system must then choose which sector protection method to use. programming (setting to ?0?) any one of the following two one-time programmable, non- volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) table 6.1. lock register for programming lock register bits refer to ta b l e 1 0 . 2 . notes 1. if the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. 2. after the lock register bits command set entry command sequence is written, reads and writes for bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. if both lock bits are selected to be programmed (to zeros) at the same time, the operation will abort. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sector can operate in any of the following three states: 1. constantly locked. the selected sectors are protected and can not be reprogrammed unless ppb lock bit is cleared via a pass word, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described in sections 6.2?6.6. 6.2 persistent protection bits the persistent protection bits are unique and nonvolatile for each sector and have the same endurances as the flash memory. preprogramming and verification prior to erasure are han- dled by the device, and therefore do not require system monitoring. notes 1. each ppb is individually programmed and all are erased in parallel. 2. entry command disables reads and writes for the bank selected. 3. reads within that bank will return the ppb status for that sector. 4. reads from other banks are allowed while writes are not allowed. device dq15-05 dq4 dq3 dq2 dq1 dq0 s29ws256n 1 1 1 password protection mode lock bit persistent protection mode lock bit customer secsi sector protection bit s29ws128n/ s29ws064n undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secsi sector protection bit
55 s29wsxxxn_m0_f0 november 4, 2004 preliminary 5. all reads must be performed using the asynchronous mode. 6. the specific sector address (a23-a14 ws256n, a22-a14 ws128n, a21-a14 ws064n) are written at the same time as the program command. 7. if the ppb lock bit is set, the ppb program or erase command will not execute and will time-out without programming or erasing the ppb. 8. there are no means for individually erasing a specific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for bank 0 10. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device as described by the flow chart below. 6.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually mod- ified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to ?1?). by issuing the dyb set or clear command sequences, the dybs will be set (programmed to ?0?) or cleared (erased to ?1?), thus placing each sector in the pro- tected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to ?0?) or cleared (erased to ?1?) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to ?1?) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to ?1?), then the sectors may be modified depending upon the ppb state of that sector (see tab l e 6 . 2 ). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to ?0?). 4. it is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dy namic sectors signify protected or unpro- tectedstate of the sectors respectively. however, if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set com- mand early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = v hh as they do when acc =v ih . 6.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (pro- grammed to ?0?), this bit locks all ppb and when cleared (programmed to ?1?), unlocks each sector. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to ?0?) only after all ppbs are configured to the desired settings.
november 4, 2004 s29wsxxxn_m0_f0 56 preliminary 6.5 password protection method the password protection method allows an even higher level of security than the persistent sector protection mode by requiring a 64 bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set ?0? to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set in order to prevent access. 2. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out with the cell as a ?0?. 3. the password is all ?1?s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1?a0) are valid during the password read, password pro- gram, and password unlock. 9. the exact password must be entered in order for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to pre- vent a hacker from running through all th e 64-bit combinations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and wr ites for other banks excluding bank 0 are allowed. 16. if the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device.
57 s29wsxxxn_m0_f0 november 4, 2004 preliminary figure 6.2. lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock data may only be progammed once. wait 4 s pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
november 4, 2004 s29wsxxxn_m0_f0 58 preliminary 6.6 advanced sector protection software examples ta b l e 6 . 2 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bit is locked (set to ?0?), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to ?1?) through a hardware reset or power cycle. see also figure 6.1 for an overview of the advanced sector protection feature. 6.7 hardware data protection methods the device offers two main types of data protection at the sector level via hardware control: ? when wp# is at v il , the four outermost sectors are locked (device specific). ? when acc is at v il , all sectors are locked. there are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. the following subsections describes these methods: 6.7.1. wp# method the write protect feature provides a hardware method of protecting the four outermost sec- tors. this function is provided by the wp# pin and overrides the previously discussed sector protection/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the ?outermost? boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 6.7.2 acc method this method is similar to above, except it protects all sectors. once acc input is set to v il , all program and erase functions are disabled and hence all sectors are protected. table 6.2. sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
59 s29wsxxxn_m0_f0 november 4, 2004 preliminary 6.7.3 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 6.7.4 write pulse ?glitch protection? noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 6.7.5 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
61 s29wsxxxn_m0_f0 november 4, 2004 preliminary 7 power conservation modes 7.1 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the de- vice is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in ?dc characteristics? represents the standby current specification 7.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the automatic sleep mode is disabled. note that a new burst operation is required to provide new data. i cc6 in ?dc characteristics? represents the automatic sleep mode current specification. 7.3 hardware reset# input operation the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the inter- nal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if re- set# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 7.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
november 4, 2004 s29wsxxxn_m0_f0 62 preliminary 8 secsi tm (secured silicon) sector flash memory region the secsi (secured silicon) sector provides an extra flash memory region that enables per- manent part identification through an electronic serial number (esn). the secsi sector is 256 words in length that consists of 128 words for factory data and 128 words for customer- secured areas. all secsi reads outside of the 256-word address range will return invalid data. the factory indicator bit, dq7, (at autoselect address 03h) is used to indicate whether or not the factory secsi sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secsi sector is locked when shipped from the factory. please note the following general conditions: ? while secsi sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secsi sector will wrap from address ffh back to address 00h. ? reads outside of sector 0 will return memory array data. ? continuous burst read past th e maximum address is undefined. ? sector 0 is remapped from memory array to secsi sector array. ? once the secsi sector entry command is issued, the secsi sector exit command must be issued to exit secsi sector mode. ? the secsi sector is not accessible when the device is executing an embedded program or embedded erase algorithm. ta b l e 8 . 1 . s e c s i tm sector addresses 8.1 factory secsi tm sector the factory secsi sector is always protected when shipped from the factory and has the fac- tory indicator bit (dq7) permanently set to a ?1?. this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre programmed with one of the following: ? a random, 8 word secure esn only within the factory secsi sector ? customer code within the customer secsi sector through the spansion tm programming service. ? both a random, secure esn and customer code through the spansion programming ser - vice. customers may opt to have their code programmed through the spansion programming ser- vices. spansion programs the customer's code, with or without the random esn. the devices are then shipped from the spansion factory with the factory secsi sector and customer secsi sector permanently locked. contact your local representative for details on using spansion programming services. sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
63 s29wsxxxn_m0_f0 november 4, 2004 preliminary 8.2 customer secsi tm sector the customer secsi sector is typically shipped unprotected (dq6 set to ?0?), allowing cus- tomers to utilize that sector in any manner they choose. if the security feature is not required, the customer secsi sector can be treated as an additional flash memory space. please note the following: ? once the customer secsi sector area is protected, the customer indicator bit will be per - manently set to ?1.? ? the customer secsi sector can be read any number of times, but can be programmed and locked only once. the customer secsi sector lock must be used with caution as once locked, there is no procedure available for unlocking the customer secsi sector area and none of the bits in the customer secsi sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when programming the customer secsi sector, but reading in banks 1 through 15 is available. ? once the customer secsi sector is locked and verified, the system must write the exit secsi sector region command sequence which return the device to the memory array at sector 0. 8.3 secsi tm sector entry and secsi sector exit command sequences the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. see command definition table [secsi tm sector command table, appendix table 10.1 for address and data requirements for both command sequences. the secsi sector entry command allows the following commands to be executed ? read customer and factory secsi areas ? program the customer secsi sector after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by sector sa0 within the memory ar- ray. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. the following are c functions and source code examples of using the secsi sector entry, pro- gram, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. note: base = base address. /* example: secsi sector entry command */ software functions and sample code table 8.2. secsi sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h
november 4, 2004 s29wsxxxn_m0_f0 64 preliminary *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ note: base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ table 8.3. secsi sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word table 8.4. secsi sector entry (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle write base + aaah base + 555h 0090h
65 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9 electrical specifications 9.1 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v io + 0.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v acc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +9.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 9.2 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9.1 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 9.1. maximum negative overshoot waveform figure 9.2. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
november 4, 2004 s29wsxxxn_m0_f0 66 preliminary 9.2 operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 v to +1.95 v v io supply voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 v to +1.95 v (contact local sales office for v io = 1.35 to +1.70 v.) notes: operating ranges define those limits between which the functionality of the device is guaranteed. 9.3 test conditions table 9.1. test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 3.0 @ 54, 66 mhz 2.5 @ 80 mhz ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under test figure 9.3. test setup
67 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9.4 key to switching waveforms 9.5 switching waveforms 9.6 v cc power-up notes: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hardware reset will be required. figure 9.5. v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 1 ms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs figure 9.4. input waveforms and measurement levels v cc v io reset# t vcs
november 4, 2004 s29wsxxxn_m0_f0 68 preliminary 9.7 dc characteristics (cmos compatible) notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io . 3. ce# must be set high when measuring the rdy pin. 4. the i cc current listed is typically less than 3 ma/mhz, with oe# at v ih . 5. i cc active while embedded erase or embedded program is in progress. 6. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 7. v ih = v cc 0.2 v and v il > ?0.1 v. 8. total current during accelerated programming is the sum of v acc and v cc currents. 9. v acc = v hh on acc input. parameter description (notes) test conditions (notes 1, 2, 9) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current (3) v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 27 54 ma 66 mhz 28 60 ma 80 mhz 30 66 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 28 48 ma 66 mhz 30 54 ma 80 mhz 32 60 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 54 mhz 29 42 ma 66 mhz 32 48 ma 80 mhz 34 54 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 32 36 ma 66 mhz 35 42 ma 80 mhz 38 48 ma i io1 v io non-active output oe# = v ih 20 30 a i cc1 v cc active asynchronous
69 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9.8 ac characteristics 9.8.1. clk characterization figure 9.6. clk characterization parameter description 54 mhz 66 mhz 80 mhz unit f clk clk frequency max 54 66 80 mhz t clk clk period min 18.5 15.1 12.5 ns t ch clk high time min 7.4 6.1 5.0 ns t cl clk low time t cr clk rise time max 3 3 2.5 ns t cf clk fall time t clk t cl t ch t cr t cf clk
november 4, 2004 s29wsxxxn_m0_f0 70 preliminary 9.8.2 synchronous/burst read notes: 1. addresses are latched on the first rising edge of clk. 2. not 100% tested. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t iacc latency max 69 ns t bacc burst access time valid clock to output delay max 13.5 11.2 9 ns t acs address setup time to clk (note 1) min 5 4 ns t ach address hold time from clk (note 1) min 7 6 ns t bdh data hold time from next clock cycle min 4 3 ns t cr chip enable to rdy valid max 13.5 11.2 9 ns t oe output enable to output valid max 13.5 11.2 ns t cez chip enable to high z (note 2) max 10 ns t oez output enable to high z (note 2) max 10 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 5 4 3.5 ns t racc ready access time from clk max 13.5 11.2 9 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 ns t avd avd# pulse min 8 ns t aoe avd low to oe# low max 38.4 ns
71 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9.8.3 timing diagrams notes: 1. figure shows total number of wait states set to five cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 9.7. clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr
november 4, 2004 s29wsxxxn_m0_f0 72 preliminary notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycl es to seven cycles. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, an d are indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. d8?df in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting addre ss in figure is the 4th address in range (0-f). figure 9.8. 8-word linear burst with wrap around notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycl es to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, an d are indicated by rdy. 3. the device is in asynchronous mode with out wrap around. 4. dc?d13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting addr ess in figure is the 1st address in range (c-13). figure 9.9. 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t aoe t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 hi-z t racc 1234567 t rdys t bacc t cr d10 t racc t aoe 7 cycles for initial access shown.
73 s29wsxxxn_m0_f0 november 4, 2004 preliminary notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has b een written with cr8=0; device will output rdy one cycle before valid data. figure 9.10. linear burst with rdy set one cycle before data 9.8.4 ac characteristics?asynchronous read note: not 100% tested. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t ce access time from ce# low max 70 ns t acc asynchronous access time max 70 ns t avdp avd# low time min 8 ns t aavds address setup time to rising edge of avd# min 4 ns t aavdh address hold time from rising edge of avd# min 7 6 ns t oe output enable to output valid max 13.5 11.2 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t cas ce# setup time to avd# min 0 ns da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 123456 t rdys t bacc t cr
november 4, 2004 s29wsxxxn_m0_f0 74 preliminary note: ra = read address, rd = read data. figure 9.11. asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas
75 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9.8.5 hardware reset (reset#) note: not 100% tested. figure 9.12. reset timings parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read (see note) min 200 ns reset# t rp ce#, oe# t rh
november 4, 2004 s29wsxxxn_m0_f0 76 preliminary 9.8.6 erase/program timing notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous program operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we#. in synchronous program operation timing, addresses are latched on the rising edge of clk. 4. see the ?erase and programming performance? section for more information. 5. does not include the preprogramming time. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t avav t wc write cycle time (note 1) min 70 ns t avwl t as address setup time (notes 2, 3) synchronous min 5ns asynchronous 0 ns t wlax t ah address hold time (notes 2, 3) synchronous min 9 ns asynchronous 20 t avdp avd# low time min 8 ns t dvwh t ds data setup time min 45 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 5 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avsc avd# setup time to clk min 5 ns t avhc avd# hold time to clk min 5 ns t csw clock setup time to we# min 5 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
77 s29wsxxxn_m0_f0 november 4, 2004 preliminary figure 9.2. chip/sector erase operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
november 4, 2004 s29wsxxxn_m0_f0 78 preliminary notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a14 for the ws064n) are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is indepe ndent of the set device read mode bit in the configuration register. figure 9.13. asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas
79 s29wsxxxn_m0_f0 november 4, 2004 preliminary notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a14 for the ws064n) are don?t care during command sequence unlock cycles. 4. addresses are latched on the first rising edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 9.14. synchronous program operation timings: clk latched addresses oe# ce# data addresses avd we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc
november 4, 2004 s29wsxxxn_m0_f0 80 preliminary note: use setup and hold times from conventional program operation. figure 9.15. accelerated unlock bypass programming timing notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. figure 9.16. data# polling timings (during embedded algorithm) ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
81 s29wsxxxn_m0_f0 november 4, 2004 preliminary notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. figure 9.17. toggle bit timings (during embedded algorithm) notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (d8 = 1 in the configuration register). when d8 = 0 in the configuration register, rdy is active one clock cycle before data. figure 9.18. synchronous data polling timings/toggle bit timings we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc
november 4, 2004 s29wsxxxn_m0_f0 82 preliminary notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device not crossing a bank in the process of performing an erase or program. 5. rdy will not go low and no additional wait states will be required if the burst frequency is <=66 mhz and the boundary crossi ng bit (d14) in the configuration register is set to 0 figure 9.20. latency with boundary crossing when frequency > 66 mhz enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 9.19. dq2 vs. dq6 clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc
83 s29wsxxxn_m0_f0 november 4, 2004 preliminary notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device crossing a bank in the process of performing an erase or program. 5. rdy will not go low and no additional wait stat es will be required if the burst frequency is < 66 mhz and the boundary crossing bit (d14) in the configuration register is set to 0. figure 9.21. latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc
november 4, 2004 s29wsxxxn_m0_f0 84 preliminary wait state configuration register setup: d13, d12, d11 = ?111? ? reserved d13, d12, d11 = ?110? ? reserved d13, d12, d11 = ?101? ? 5 programmed, 7 total d13, d12, d11 = ?100? ? 4 programmed, 6 total d13, d12, d11 = ?011? ? 3 programmed, 5 total d13, d12, d11 = ?010? ? 2 programmed, 4 total d13, d12, d11 = ?001? ? 1 programmed, 3 total d13, d12, d11 = ?000? ? 0 programmed, 2 total note: figure assumes address d0 is not at an address boundary, and wait state is set to ?101?. figure 9.22. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
85 s29wsxxxn_m0_f0 november 4, 2004 preliminary note: breakpoints in waveforms indicate that system may alte rnately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid information. figure 9.23. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
november 4, 2004 s29wsxxxn_m0_f0 86 preliminary 9.8.7 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. typical chip programming time is considerably less than the maximum chip programming time listed, and is based on single word programming. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see the appendix for further information on command definitions. 6. contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. 7. refer to application note ?erase suspend/resume timing? for more details. 8. word programming specification is based upon a single word programming operation not utilizing the write buffer. parameter typ (note 1) max (note 2) unit comments sector erase time 64 kword v cc 0.6 3.5 s excludes 00h programming prior to erasure (note 4) 16 kword v cc <0.15 2 chip erase time v cc 153.6 (ws256n) 77.4 (ws128n) 39.3 (ws064n) 308 (ws256n) 154 (ws128n) 78 (ws064n) s acc 130.6 (ws256n) 65.8 (ws128n) 33.4 (ws064n) 262 (ws256n) 132 (ws128n) 66 (ws064n) single word programming time (note 8) v cc 40 400 s acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time (note 3) v cc 157.3 (ws256n) 78.6 (ws128n) 39.3 (ws064n) 314.6 (ws256n) 157.3 (ws128n) 78.6 (ws064n) s excludes system level overhead
87 s29wsxxxn_m0_f0 november 4, 2004 preliminary 9.8.8 bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c; f = 1.0 mhz. parameter symbol parameter description test setup typ. max unit c in input capacitance v in = 0 5.3 6.3 pf c out output capacitance v out = 0 5.8 6.8 pf c in2 control pin capacitance v in = 0 6.3 7.3 pf
november 4, 2004 s29wsxxxn_m0_f0 88 preliminary 10 appendix this section contains information relating to software control or interfacing with the flash de- vice. for additional information and assistance regarding software, see the additional resources section on page 18, or explore the web at www.amd.com and www.fujitsu.com.
89 s29wsxxxn_m0_f0 november 4, 2004 preliminary table 10.1. memory array commands command sequence (notes) cycles bus cycles (notes 1?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (6) 1 ra rd reset (7) 1 xxx f0 auto- select (8) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id (9) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e ba+x0e data ba+x0f 2200 indicator bits (10) 4 555 aa 2aa 55 [ba]555 90 [ba]x03 data program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (11) 6 555 aa 2aa 55 pa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (12) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend (13) 1 ba b0 erase/program resume (14) 1 ba 30 set configuration register (18) 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr cfi query (15) 1 [ba]555 98 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program (16) 2 xxx a0 pa pd cfi (16) 1 xxx 98 reset 2 xxx 90 xxx 00 secsi sector entry 3 555 aa 2aa 55 555 88 program (17) 4 555 aa 2aa 55 555 a0 pa pd read (17) 1 00 data exit (17) 4 555 aa 2aa 55 555 90 xxx 00 legend: x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of the avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. ws256n = a23?a14; ws128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. cr = configuration register data bits d15?d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 5.4 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 6. no unlock or command cycles required when bank is reading array data. 7. reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the system must provide the bank address. see autoselect section for more information . 9. data in cycle 5 is 2230 (ws256n), 2232 (ws064n), or 2231 (ws128n). 10. see table 5.16 for indicator bit values. 11. total number of cycles in the command sequence is determined by the number of words written to the write buffer. the number of cycles in the command sequence is 37 for full page programming (32 words). less than 32 word programming is not recommended. 12. command sequence resets device for next command after write- to-buffer operation. 13. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. erase resume command is valid only during the erase suspend mode, and requires the bank address. 15. command is valid when device is ready to read array data or when device is in autoselect mode. address will equal 55h on all future devices, but 555h for ws256n/128n/064n. 16. requires entry command sequence prior to execution. unlock bypass reset command is required to return to reading array data. 17. requires entry command sequence prior to execution. secsi sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. requires reset command to configure the configuration register.
november 4, 2004 s29wsxxxn_m0_f0 90 preliminary table 10.2. sector protection commands command sequence (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry (5) 3 555 aa 2aa 55 555 40 program (6) 2 xx a0 77 data read (6) 1 77 data command set exit (7) 2 xx 90 xx 00 password protection command set entry (5) 3 555 aa 2aa 55 555 60 program [0-3] (8) 2 xx a0 00 pwd[0-3] read (9) 4 0...00 pwd0 0...01 pwd1 0...02 pwd2 0...03 pwd3 unlock 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit (7) 2 xx 90 xx 00 non-volatile sector protection (ppb) command set entry (5) 3 555 aa 2aa 55 [ba]555 c0 ppb program (10) 2 xx a0 sa 00 all ppb erase (10, 11) 2 xx 80 00 30 ppb status read 1 sa rd(0) command set exit (7) 2 xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry (5) 3 555 aa 2aa 55 [ba]555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 ba rd(0) command set exit (7) 2 xx 90 xx 00 volatile sector protection (dyb) command set entry (5) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit (7) 2 xx 90 xx 00 l egen d : x = don?t care. ra = address of the memory location to be read. pd(0) = secsi sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lock bit. pd(1), or bit[1], must be set to ?0? for protection while pd(2), bit[2] must be left as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd(1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = sector address. ws256n = a23?a14; ws128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0), rd(1), rd(2) = dq0, dq1, or dq2 protection indicator bit. if protected, dq0, dq1, or dq2 = 0. if unprotected, dq0, dq1, dq2 = 1. notes: 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. if both the persistent protection mode locking bit and the password protection mode locking bit are set at the same time, the command operation will abort and return the device to the default persistent sector protection mode during 2nd bus cycle. note that on all future devices, addresses will equal 00h, but are currently 77h for ws256n, ws128n, and ws064n. see tables 6.1 and 6.2 for explanation of lock bits. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. see figure 6.2 for details. 11. ?all ppb erase? command will pre-program all ppbs before erasure to prevent over-erasure.
91 s29wsxxxn_m0_f0 november 4, 2004 preliminary 10.1 common flash memory interface the common flash interface (cfi) specification outlines device and host system software in- terrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back-ward-compatible for the specified flash device fami- lies. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 10.3?10.6 ) within that bank. all reads out- side of the cfi address range, within the bank, will return non-valid data. reads from other banks are allowed, writes are not. to terminate reading cfi data, the system must write the reset command. the following is a c source code example of using the cfi entry and exit functions. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, please refer to the cfi specification (see jedec publications jep137- a and jesd68.01and cfi publication 100). please contact your sales office for copies of these documents. table 10.3. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
november 4, 2004 s29wsxxxn_m0_f0 92 preliminary table 10.4. system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0004h max. timeout for buffer write 2 n times typical 25h 0003h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 10.5. device geometry definition addresses data description 27h 0019h (ws256n) 0018h (ws128n) 0017h (ws064n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws256n) 007dh (ws128n) 003dh (ws064n) erase block region 2 information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
93 s29wsxxxn_m0_f0 november 4, 2004 preliminary table 10.6. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0100h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0100 = 0.11 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00f3h (ws256n) 006fh (ws128n) 0037h (ws064n) simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = dual boot device 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0007h secsi sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n ns 56h 0005h program suspend time-out maximum 2 n ns 57h 0010h bank organization: x = number of banks 58h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 0 region information. x = number of sectors in bank
november 4, 2004 s29wsxxxn_m0_f0 94 preliminary 59h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 1 region information. x = number of sectors in bank 5ah 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 2 region information. x = number of sectors in bank 5bh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 3 region information. x = number of sectors in bank 5ch 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 4 region information. x = number of sectors in bank 5dh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 5 region information. x = number of sectors in bank 5eh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 6 region information. x = number of sectors in bank 5fh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 7 region information. x = number of sectors in bank 60h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 8 region information. x = number of sectors in bank 61h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 9 region information. x = number of sectors in bank 62h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 10 region information. x = number of sectors in bank 63h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 11 region information. x = number of sectors in bank 64h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 12 region information. x = number of sectors in bank 65h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 13 region information. x = number of sectors in bank 66h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 14 region information. x = number of sectors in bank 67h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 15 region information. x = number of sectors in bank table 10.6. primary vendor-specific extended query (continued) addresses data description
95 s29wsxxxn_m0_f0 november 4, 2004 preliminary 11 commonly used terms term definition acc accelerate. a special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above v cc . in some devices acc may protect all sectors when at a low voltage. a max most significant bit of the address input [a23 for 256mbit, a22 for128mbit, a21 for 64mbit] a min least significant bit of the address input signals (a0 for all devices in this document). asynchronous operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. autoselect read mode for obtaining manufacturer and device information as well as sector protection status. bank section of the memory array consisting of multiple consecutive sectors. a read operation in one bank, can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. boot sector smaller size sectors located at the top and or bottom of flash device address space. the smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. boundary location at the beginning or end of series of memory locations. burst read see synchronous read . byte 8 bits cfi common flash interface. a flash memory industry standard specification [jedec 137- a and jesd68.01] designed to allow a system to interrogate the flash to determine its size, type and other performance parameters. clear zero (logic low level) configuration register special purpose register which must be programmed to enable synchronous read mode continuous read synchronous method of burst read whereby the device will read continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address erase returns bits of a flash memory array to their default state of a logical one (high level). erase suspend/erase resume halts an erase operation to allow reading or programming in any sector that is not selected for erasure bga ball grid array package. spansion llc offers two variations: fortified ball grid array and fine-pitch ball grid array. see the specific package drawing or connection diagram for further details. linear read synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address . mcp multi-chip package. a method of combining integrated circuits in a single package by ?stacking? multiple die of the same or different devices. memory array the programmable area of the product available for data storage. mirrorbit? technology spansion? trademarked technology for storing multiple bits of data in the same transistor.
november 4, 2004 s29wsxxxn_m0_f0 96 preliminary page group of words that may be accessed more rapidly as a group than if the words were accessed individually. page read asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less ?page? access time to be read. different words in the group are accessed by changing only the least significant address lines. password protection sector protection method which uses a programmable password, in addition to the persistent protection method, for protection of sectors in the flash memory device . persistent protection sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the flash memory device. this method replaces a prior technique of requiring a 12v supply to control the protection method. program stores data into a flash memory by selectively clearing bits of the memory array in order to leave a data pattern of ?ones? and ?zeros?. program suspend/program resume halts a programming operation to read data from any location that is not selected for programming or erase. read host bus cycle that causes the flash to output data onto the data bus. registers dynamic storage bits for holding device control information or tracking the status of an operation. secsi? secured silicon. an area consisting of 256 bytes in which any word may be programmed once, and the entire area may be protected once from any future programming. information in this area may be programmed at the factory or by the user. once programmed and protected there is no way to change the secured information. this area is often used to store a software readable identification such as a serial number. sector protection use of one or more control bits per sector to indicate whether each sector may be programmed or erased. if the protection bit for a sector is set the embedded algorithms for program or erase will ignore program or erase commands related to that sector. sector an area of the memory array in which all bits must be erased together by an erase operation. simultaneous operation mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank. reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. synchronous operation operation that progresses only when a timing signal, known as a clock, transitions between logic levels (that is, at a clock edge). versatileio? (v io ) separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. unlock bypass mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command. in this mode the initial two ?unlock? write cycles, of the usual 4 cycle program command, are not required ? reducing all program commands to two bus cycles while in this mode. word two contiguous bytes (16 bits) located at an even byte boundary. a double word is two contiguous words located on a two word boundary. a quad word is four contiguous words located on a four word boundary. term definition
97 s29wsxxxn_m0_f0 november 4, 2004 preliminary wraparound special burst read mode where the read address ?wraps? or returns back to the lowest address boundary in the selected range of words, after reading the last byte or word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. write interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. the term write is often associated with ?writing command cycles? to enter or exit a particular mode of operation. write buffer multi-word area in which multiple words may be programmed as a single operation . a write buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. write buffer programming method of writing multiple words, up to the maximum size of the write buffer, in one operation. using write buffer programming will result in 8 times faster programming time than by using single word at a time programming commands. write operation status allows the host system to determine the status of a program or erase operation by reading several special purpose register bits . term definition
july 30, 2004 psram_type04_17a0 psram type 4 98 preliminary psram type 4 8m x 16-bit synchronous burst psram features ? process technology: cmos ? organization: 8m x16 bit ? power supply voltage: 1.7~2.0v ? three state outputs ? supports mrs (mode register set) ? mrs control - mrs pin control ? supports power saving modes - partial array refresh mode internal tcsr ? supports driver strength optimization for system environment power saving ? supports asynchronous 4-page read and asynchronous write operation ? supports synchronous burst read and asynchronous write operation (ad - dress latch type and low adv type) ? supports synchronous burst read and synchronous burst write operation ? synchronous burst (read/write) operation ? supports 4 word / 8 word / 16 word and full page(256 word) burst ? supports linear burst type & interleave burst type ?latency support: latency 5 @ 66mhz(tcd 10ns) latency 4 @ 54mhz(tcd 10ns) ? supports burst read suspend in no clock toggling ? supports burst write data masking by /ub & /lb pin control ? supports wait pin function for indicating data availability. ? max. burst clock frequency: 66mhz pin description pin name function ty p e description clk clock input commands are referenced to clk adv# address valid valid address is latched by adv falling edge mrs# mode register set mrs# low enables mode register to be set cs# chip select cs# low enables the chip to be active cs# high disables the chip and puts it into standby mode oe# output enable oe# low enables the chip to output the data we# write enable we# low enables the chip to start writing the data lb# lower byte (i/o 0~7 ) ub# (lb#) low enables upper byte (lower byte) to start operating ub# upper byte (i/o 8~15 ) a0-a22 address 0 ~ address 22 valid addresses input when adv is low mode setting input when mrs is low i/o0-i/o15 data inputs / outputs input/output depending on ub# or lb# status, word (16-bit, ub# & lb# low) data, upper byte (8-bit, ub# low & lb# high) data or lower byte (8-bit, lb# low & ub# high) data is loaded
99 psram type 4 psram_type04_17a0 july 30, 2004 preliminary power up sequence after applying v cc up to minimum operating voltage (1.7v), drive cs# high first and then drive mrs# high. this gets the device into power up mode. wait 200 s minimum to get into the normal operation mode. during power up mode, the standby current cannot be guaranteed. to obtain stable standby current levels, at least one cycle of active operation should be implemented regardless of wait time duration. to obtain appropriate device operation, be sure to follow the proper power up sequence. 1. apply power. 2. maintain stable power (v cc min.=1.7v) for a minimum 200 s with cs# and mrs# high. v cc voltage source power core power supply v ccq voltage source power i/o power supply v ss ground source gnd core ground source v ssq i/o ground source gnd i/o ground source wait# valid data indicator output wait# indicates whether data is valid or not pin name function type description
july 30, 2004 psram_type04_17a0 psram type 4 100 preliminary timing diagrams power up notes: 1. after v cc reaches v cc (min.), wait 200 s with cs# and mrs# high. this puts the device into normal operation. standby mode the default mode after power up is asynchronous mode (4 page read and asyn - chronous write). but this default mode is not 100% guaranteed, so the mrs# setting sequence is highly recommended after power up. for entry to par mode, drive the mrs# pin into v il for over 0.5s or longer (sus - pend period) during standby mode after the mrs# setting has been completed (a4=1, a3=0). if the mrs# pin is driven into v ih during par mode, the device reverts to standby mode without the wake up sequence. figure 11.24. power up timing figure 11.25. standby mode state machines ~ ~ v cc v cc(min) min. mrs# cs# min. 0ns power up mode min. 0ns normal operation 200 s 200 s ~ ~ ~ ~ active standby mode par mode mrs setting cs# = v ih mrs# = v ih cs# = ub# = lb# = v il we# = v il , mrs# = v ih cs# = v il , ub# or lb# = v il mrs# = v ih cs# = v ih mrs# = v ih mrs# = v il cs# = v il we# = v il , mrs#=v il mrs setting initial state (wait 200s) power on
101 psram type 4 psram_type04_17a0 july 30, 2004 preliminary functional description ta b l e 1 1 . 7 . asynchronous 4 page read & asynchronous write mode (a15/a14=0/0) legend: x = don?t care (must be low or high state). notes: 1. in asynchronous mode, clock and adv# are ignored. 2. the wait# pin is high-z in asynchronous mode. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 power deselected h hxxxxhigh-zhigh-zstandby deselected h l xxxxhigh-zhigh-zpar output disabled l h h h x x high-z high-z active outputs disabled l h x x h h high-z high-z active lower byte read l hlhlh d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l hhl lh d in high-z active upper byte write l h h l h l high-z d in active word write l hhlll d in d in active mode register set l l h l l l high-z high-z active
july 30, 2004 psram_type04_17a0 psram type 4 102 preliminary table 11.8. synchronous burst read & asynchronous write mode (a15/a14=0/1) notes: 1. x must be low or high state. 2. x means ?don?t care? (can be low, high or toggling). 3. wait# is the device output signal and does not have any affect on the mode definition. please refer to each timing diagram for wait# pin function. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x x x x high-z high-z x (note 2) x (note 2) standby deselected h l x x x x high-z high-z x (note 2) x (note 2) par output disabled l h h h x x high-z high-z x (note 2) hactive outputs disabled l h x x h h high-z high-z x (note 2) hactive read command l h x h x x high-z high-z active lower byte read l h l h l h d out high-z hactive upper byte read l h l h h l high-z d out hactive word read l h lhll d out d out hactive lower byte write l h h l l h d in high-z x (note 2) active upper byte write l h h l h l high-z d in x (note 2) active word write l h h l l l d in d in x (note 2) active mode register set l l h l l l high-z high-z x (note 2) active or or or or
103 psram type 4 psram_type04_17a0 july 30, 2004 preliminary ta b l e 1 1 . 9 . synchronous burst read & synchronous burst write mode(a15/a14=1/0) notes: 1. x must be low or high state. 2. x means ?don?t care? (can be low, high or toggling). 3. wait# is the device output signal and does not have any affect on the mode definition. please refer to each timing diagram for wait# pin function. mode register setting operation the device has several modes: ? asynchronous page read mode ? asynchronous write mode ? synchronous burst read mode ? synchronous burst write mode ? standby mode and partial array refresh (par) mode. partial array refresh (par) mode is defined through the mode register set (mrs) option. the mrs option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode. mode cs# mrs# oe# we# lb# ub# i/o 0-7 i/o 8-15 clk adv# power deselected h h x (note1) x (note1) x (note1) x (note1) high-z high-z x (note 2) x (note 2) standby deselected h l x (note1) x (note1) x (note1) x (note1) high-z high-z x (note 2) x (note 2) par output disabled l h h h x x high-z high-z x (note 2) hactive outputs disabled lh x (note1) x (note1) h h high-z high-z x (note 2) hactive read command lh x (note1) h x x high-z high-z active lower byte read lh l h l h d out high-z hactive upper byte read lh l h h lhigh-zd out hactive word read l h l h l l d out d out hactive write command lh x (note1) high-z high-z active lower byte write lh h x (note1) lhd in high-z hactive upper byte write lh h x (note1) hlhigh-zd in hactive word write l h h x (note1) lld in d in hactive mode register set ll h l l high-z high-z active or l or l
july 30, 2004 psram_type04_17a0 psram type 4 104 preliminary mode register set (mrs) the mode register stores the data for controlling the various operation modes of the psram. it programs partial array refresh (par), burst length, burst type, la - tency count and various vendor specific options to make psram useful for a variety of different applications. the default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. the mode register is written by driving cs#, adv#, we#, ub#, lb# and mrs# to v il and driving oe# to v ih during valid addressing. the mode register is di - vided into various fields depending on the fields of functions. the par field uses a0~a4, burst length field uses a5~a7, burst type uses a8, latency count uses a9~a11, wait polarity uses a13, operation mode uses a14~a15 and driver strength uses a16~a17. refer to the table below for detailed mode register settings. a18~a22 addresses are ?don?t care? in the mode register setting. ta b l e 1 1 . 1 0 . mode register setting according to field of function note: ds (driver strength), ms (mode select), wp (wait polarity ), latency (latency count), bt (burst type), bl (burst length), par (partial array refresh), para (partial array refresh array), pars (partial array refresh size), rfu (re - served for future use). ta b l e 1 1 . 1 1 . mode register set address a17-a16 a15-a14 a13 a12 a11-a19 a8 a7-a5 a4-a3 a2 a1-a0 function ds ms wp rfu latency bt bl par para pars driver strength mode select a17 a16 ds a15 a14 ms 0 0 full drive (note 1) 0 0 async. 4 page read / async. write (note 1) 0 1 1/2 drive 0 1 sync. burst read / async. write 1 0 1/4 drive 1 0 sync. burst read / sync. burst write wait# polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl 0 low enable (note 1) 0 must (note 1) 0 0 0 3 0 linear (note 1) 0 1 0 4 word 1 high enable 1 ? 0 0 1 4 1 interleave 0 1 1 8 word 0 1 0 5 1 0 0 16 word (note 1) 0 1 1 6 1 1 1 full (256 word)
105 psram type 4 psram_type04_17a0 july 30, 2004 preliminary notes: 1. default mode. the address bits other than those listed in the table above are reserved. for example, burst length address bits(a7:a6:a5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. if the reserved address bits are input, then the mode will be set to the default mode. each field has its own default mode, but this default mode is not 100% guaranteed, so the mrs setting sequence is highly recommended after power up. a12 is a reserved bit for future use. a12 must be set as ?0?. not all the mode settings are tested. per the mode settings to be tested, pl ease contact spansion. the 256 word full page burst mode needs to meet t bc (burst cycle time) parameter as max. 2500ns. mrs pin control type mode register setting timing in this device, the mrs pin is used for two purposes. one is to get into the mode register setting and the other is to execute partial array refresh mode. to get into the mode register setting, the system must drive the mrs# pin to v il and immediately (within 0.5s) issue a write command (drive cs#, adv#, ub#, lb# and we# to v il and drive oe# to v ih during valid address). if the subse - quent write command (we# signal input) is not issued within 0.5s, then the device may get into the par mode. partial array refresh pa r a r r ay pa r s i ze a4 a3 par a2 pa ra a1 a0 pa r s 1 0 par enable 0 bottom array (note 1) 0 0 full array (note 1) 1 1 par disable (note 1) 1 to p ar r a y 0 1 3/4 array 1 0 1/2 array 1 1 1/4 array
july 30, 2004 psram_type04_17a0 psram type 4 106 preliminary table 11.12. mrs ac characteristics note: v cc =1.7~2.0v, t a =-40 to 85c, maximum main clock frequency=66mhz figure 11.26. mode register setting timing (oe# = v ih ) parameter list symbol speed units min max mrs mrs# enable to register write start t mw 0 500 ns end of write to mrs# disable t wu 0 ? ns t wu address we# t wc t cw t aw t bw t wp t as cs# t mw adv# mrs# 12345678910111213 clk 0 (mrs setting timing) 1. clock input is ignored. ub#, lb# register write start register write complete register update complete
107 psram type 4 psram_type04_17a0 july 30, 2004 preliminary asynchronous operation asynchronous 4 page read operation asynchronous normal read operation starts when cs#, oe# and ub# or lb# are driven to v il under the valid address without toggling page addresses (a0, a1). if the page addresses (a0, a1) are toggled under the other valid address, the first data will be out with the normal read cycle time (trc) and the second, the third and the fourth data will be out with the page cycle time (tpc). (mrs# and we# should be driven to v ih during the asynchronous (page) read operation) clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. asynchronous write operation asynchronous write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid address. mrs# and oe# should be driven to v ih during the asynchronous write operation. clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. asynchronous write operation in synchronous mode a write operation starts when cs#, we# and ub# or lb# are driven to v il under the valid address. clock input does not have any affect to the write operation (mrs# and oe# should be driven to v ih during write operation. adv# can be ei - ther toggling for address latch or held in v il ). clock, adv#, wait# signals are ignored during the asynchronous (page) read operation. figure 11.27. asynchronous 4-page read figure 11.28. asynchronous write a1~a0 cs# oe# a22~a2 ub#, lb# data out high-z high- z high-z address cs# we# data in data out ub#, lb#
july 30, 2004 psram_type04_17a0 psram type 4 108 preliminary synchronous burst operation burst mode operations enable the system to get high performance read and write operation. the address to be accessed is latched on the rising edge of clock or adv# (whichever occurs first). cs# should be setup before the address latch. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# high) or a write (we# low). for the optimized burst mode of each system, the system should determine how many clock cycles are required for the first data of each burst access (latency count), how many words the device outputs during an access (burst length) and which type of burst operation (burst type: linear or interleave) is needed. the wait polarity should also be determined (see table 11.11 ). synchronous burst read operation the synchronous burst read command is implemented when the clock rising is detected during the adv# low pulse. adv# and cs# should be set up before the clock rising. during the read command, we# should be held in v ih . the multiple clock risings (during the low adv# period) are allowed, but the burst operation starts from the first clock rising. the first data will be out with latency count and t cd . synchronous burst write operation the synchronous burst write command is implemented when the clock rising is detected during the adv# and we# low pulse. adv#, we# and cs# should be set up before the clock rising. the multiple clock risings (during the low adv# period) are allowed but, the burst operation starts from the first clock rising. the first data will be written in the latency clock with t ds . note: latency 5, bl 4, wp: low enable figure 11.29. synchronous burst read clk adv# addr. oe# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ub#, lb# wait# data out
109 psram type 4 psram_type04_17a0 july 30, 2004 preliminary note: latency 5, bl 4, wp: low enable synchronous burst operation terminology clock (clk) the clock input is used as the reference for synchronous burst read and write op - eration of the psram. the synchronous burst read and write operations are synchronized to the rising edge of the clock. the clock transitions must swing be - tween v il and v ih . latency count the latency count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. this value depends on the input clock frequency. ta b l e 1 1 . 1 3 shows the sup - ported latency count. ta b l e 1 1 . 1 3 . latency count support ta b l e 1 1 . 1 4 . number of clocks for 1st data figure 11.30. synchronous burst write clock frequency up to 66 mhz up to 54 mhz up to 40 mhz latency count 5 4 3 set latency latency 3 latency 4 latency 5 # of clocks for 1st data (read) 4 5 6 # of clocks for 1st data (write) 2 3 4 clk adv# addr . we# cs# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 wait# data in ub#, lb#
july 30, 2004 psram_type04_17a0 psram type 4 110 preliminary note: the first data will always keep the latency. from the second data on, some period of wait time may be caused by wait# pin. burst length burst length identifies how many data the device outputs during an access. the device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word full page burst mode needs to meet t bc (burst cycle time) parameter as 2500ns max. the first data will be output with the set latency + t cd . from the second data on, the data will be output with t cd from each clock. burst stop burst stop is used when the system wants to stop burst operation on purpose. if driving cs# to v ih during the burst read operation, the burst operation is stopped. during the burst read operation, the new burst operation cannot be is - sued. the new burst operation can be issued only after the previous burst operation is finished. the burst stop feature is very useful because it enables the user to utilize the un- supported burst length such as 1 burst or 2 burst, used mostly in the mobile handset application environment. synchronous burst operation terminology wait control (wait#) the wait# signal is the device?s output signal that indicates to the host system when it?s data-out or data-in is valid. to be compatible with the flash interfaces of various microprocessor types, the wait# polarity (wp) can be configured. the polarity can be programmed to be either low enable or high enable. for the timing of wait# signal, the wait# signal should be set active one clock prior to the data regardless of read or write cycle. figure 11.31. latency configuration (read) address data out adv# clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t
111 psram type 4 psram_type04_17a0 july 30, 2004 preliminary note: latency: 5, burst length: 4, wp: low enable burst type the device supports linear type burst sequence and interleave type burst se - quence. linear type burst sequentially increments the burst address from the starting address. the detailed linear and interleave type burst address sequence is shown in table 11.15 . ta b l e 1 1 . 1 5 . burst sequence figure 11.32. wait# and read/write latency control start address burst address sequence (decimal) wrap (note 1) 4 word burst 8 word burst 16 word burst full page(256 word) linear interleave linear interleave linear interleave linear 0 0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1 -2-...-14-15 0-1-2-3-4...14-15 0-1-2-...-254-255 1 1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6 1-2-3-...-15-0 1-0-3-2-5...15-14 1-2-3-...-255-0 2 2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5 2-3-4-...-0-1 2-3-0-1-6...12-13 2-3-4-...-255-0-1 3 3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4 3-4 -5-...-1-2 3-2-1-0-7...13-12 3-4-5-...-255-0-1-2 4 4-5-...-1-2-3 4-5-6-...-2-3 4-5-6-...-2-3 4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3 5 5-6-...-2-3-4 5-4-7-...-3-2 5-6-7-...-3-4 5-4-7-6-1...11-10 5-6-7-...-255-...-3-4 6 6-7-...-3-4-5 6-7-4-...-0-1 6-7-8-...-4-5 6-7-4-5-2...8-9 6-7-8-...-255-...-4-5 7 7-0-...-4-5-6 7-6-5-...-1-0 7-8-9-...-5-6 7-6-5-4-3...9-8 7-8-9-...-255-...-5-6 ~ ~~ ~ 14 14-15-0-...-12-13 14-15-12-...- 0-1 14-15-...-255-...-12-13 15 15-0-1-...-13-14 15-14-13-...- 1-0 15-16-...-255-...-13-14 ~ ~ 255 255-0-1-...-253-254 12345678910111213 adv# read clk dq0 dq1 0 dq2 write d0 d1 d2 dq3 d3 data out data in cs# latency 5 latency 5 high-z wait# high-z wait#
july 30, 2004 psram_type04_17a0 psram type 4 112 preliminary low power features internal tcsr the internal temperature compensated self refresh (tcsr) feature is a very useful tool for reducing standby current at room temperature (below 40c). dram cells have weak refresh characteristics in higher temperatures. high tem - peratures require more refresh cycles, which can lead to standby current increase. without the internal tcsr, the refresh cycle should be set at worst condition so as to cover the high temperature (85c) refresh characteristics. but with internal tcsr, a refresh cycle below 40c can be optimized, so the standby current at room temperature can be greatly reduced. this feature is beneficial since most mobile phones are used at or below 40c in the phone standby mode. ta b l e 1 1 . 1 6 . par mode characteristics notes: 1. only the data in the refreshed block are valid. 2. the par array can be selected through mode register set (see ?mode register setting operation? on page 103). driver strength optimization the optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. through this driver strength op - timization, the device can minimize the noise generated on the data bus during read operation. the device supports full drive, 1/2 drive and 1/4 drive. partial array refresh (par) mode the par mode enables the user to specify the active memory array size. the psram consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays through the mode register setting. the active memory array is periodically refreshed whereas the disabled array is not re - freshed, so the previously stored data is lost. even though par mode is enabled through the mode register setting, par mode execution by the mrs# pin is still needed. the normal operation can be execut ed even in refresh-disabled array as long as the mrs# pin is not driven to the low condition for over 0.5s. driving the mrs# pin to the high condition puts the device back to the normal operation figure 11.33. par mode execution and exit power mode address (bottom array) (note 2) address (top array) (note 2) memory cell data standby current (a, max) wait time (s) standby (full array) 000000h ~ 7fffffh 000000h ~ 7fffffh valid (note 1) 200 0 partial refresh(3/4 block) 000000h ~ 5fffffh 200000h ~ 7fffffh 170 partial refresh(1/2 block) 000000h ~ 3fffffh 400000h ~ 7fffffh 150 partial refresh(1/4 block) 000000h ~ 1fffffh 600000h ~ 7fffffh 140 mrs# mode cs# normal operation 0.5 s suspend par mode normal operation
113 psram type 4 psram_type04_17a0 july 30, 2004 preliminary mode from the par executed mode. refer to figure 11.33 and ta b l e 1 1 . 1 6 for par operation and par address mapping. absolute maximum ratings notes: 1. stresses greater than those listed under " absolute maximum ratings " section may cause permanent damage to the device. functional operation should be restricted to use under recommended operating conditions only. exposure to absolute maximum rating conditions longer than one second may affect reliability. dc recommended operating conditions notes: 1. ta=-40 to 85c, unless otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc +0.3v v power supply voltage relative to v ss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c symbol parameter min ty p max unit v cc power supply voltage 1.7 1.85 2.0 v v ss ground 0 0 0 v ih input high voltage 0.8 x v cc ? v cc + 0.2 (note 2) v il input low voltage -0.2 (note 3) ? 0.4 symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c io input/output capacitance v out = 0v ? 10 pf
july 30, 2004 psram_type04_17a0 psram type 4 114 preliminary dc and operating characteristics common notes: 1. full array partial refresh current (i sbp ) is same as standby current (i sb1 ). item symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs#=v ih , mrs#=v ih , oe#=v ih or we#=v il , v io =v ss to v cc -1 ? 1 a average operating current i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs#=v il , mrs#=v ih , v in =v il or v ih ??40ma output low voltage v ol i ol =0.1ma ? ? 0.2 v output high voltage v oh i oh =-0.1ma 1.4 ? ? v standby current (cmos) i sb1 cs# v cc -0.2v, mrs# v cc -0.2v, other inputs = v ss to v cc < 40c ? ? tbd a < 85c ? ? 200 a partial refresh current i sbp (note 1) mrs# 0.2v, cs# v cc -0.2v other inputs = v ss to v cc < 40c 3/4 block ? ? tbd a 1/2 block ? ? tbd 1/4 block ? ? tbd < 85c 3/4 block ? ? 170 a 1/2 block ? ? 150 1/4 block ? ? 140
115 psram type 4 psram_type04_17a0 july 30, 2004 preliminary ac operating conditions test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 11.34 ): cl=50pf figure 11.34. output load 50 dout 30pf z0= 50 vtt = 0.5 x v ddq
july 30, 2004 psram_type04_17a0 psram type 4 116 preliminary asynchronous ac characteristics (v cc =1.7~2.0v, ta=-40 to 85 c) notes: 1. t wp (min)=70ns for continuous write operation over 50 times. symbol parameter speed bins unit min max read t rc read cycle time 70 ? ns t pc page read cycle time 25 ? ns t aa address access time ? 70 ns t pa page access time ? 20 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 35 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 5 ? ns t olz output enable to low-z output 5 ? ns t chz chip disable to high-z output 0 7 ns t bhz ub#, lb# disable to high-z output 0 7 ns t ohz output disable to high-z output 0 7 ns t oh output hold 3 ? ns write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t adv adv# minimum low pulse width 7 ? ns t as address set-up time to beginning of write 0 ? ns t as(a) address set-up time to adv# falling 0 ? ns t ah(a) address hold time from adv# rising 7 ? ns t css(a) cs# setup time to adv# rising 10 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 (note 1) ? ns t whp we# high pulse width 5 ns latency-1 clock ? t wr write recovery time 0 ? ns t wlrl we# low to read latency 1 ? clock t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns
117 psram type 4 psram_type04_17a0 july 30, 2004 preliminary timing diagrams asynchronous read timing waveform mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous read cycle, clock, adv# and wait# signals are ignored. ta b l e 1 1 . 1 7 . asynchronous read ac characteristics figure 11.35. timing waveform of asynchronous read cycle symbol speed units symbol speed units min max min max t rc 70 ? ns t olz 5 ? ns t aa ? 70 t blz 5 ? t co ? 70 t lz 10 ? t ba ? 35 t chz 0 7 t oe ? 35 t bhz 0 7 t oh 3 ? t ohz 0 7 data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t chz t co cs# oe# ub#, lb# address data out
july 30, 2004 psram_type04_17a0 psram type 4 118 preliminary page read mrs# = v ih , we# = v ih , wait# = high-z notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t chz(max.) is less than t lz(min.) both for a given device and from device to device interconnection. 3. in asynchronous 4 page read cycle, clock, adv# and wait# signals are ignored. ta b l e 1 1 . 1 8 . asynchronous page read ac characteristics figure 11.36. timing waveform of page read cycle symbol speed units symbol speed units min max min max t rc 70 ? ns t oh 3 ? ns t aa ? 70 t olz 5 ? t pc 25 ? t blz 5 ? t pa ? 20 t lz 10 ? t co ? 70 t chz 0 7 t ba ? 35 t bhz 0 7 t oe ? 35 t ohz 0 7 data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa a22~a2 a1~a0 cs# oe# t ohz t oe t co t aa data out t chz t oh t bhz t ba t olz t blz high z t lz t rc ub#, lb#
119 psram type 4 psram_type04_17a0 july 30, 2004 preliminary asynchronous write timing waveform asynchronous write cycle - we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. ta b l e 1 1 . 1 9 . asynchronous write ac characteristics notes: 1. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.37. timing waveform of write cycle symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0 ? ns t cw 60 ? t wr 0 ? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0 ? t wp 55 (note 1) ? address we# d ata i n t wc t cw t aw t bw t wp t as t dh t dw high-z high-z data valid cs# t wr data out high- z high-z ub#, lb#
july 30, 2004 psram_type04_17a0 psram type 4 120 preliminary write cycle 2 mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 5. in asynchronous write cycle, clock, adv# and wait# signals are ignored. ta b l e 1 1 . 2 0 . asynchronous write ac characteristics (ub# & lb# controlled) notes: 1. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.38. timing waveform of write cycle(2) symbol speed units symbol speed units min max min max t wc 70 ? ns t as 0 ? ns t cw 60 ? t wr 0 ? t aw 60 ? t dw 30 ? t bw 60 ? t dh 0 ? t wp 55 (note 1) ? address data valid we# data in data out high-z high- z t wc t cw t bw t wp t dh t dw t wr t aw t as cs# ub#, lb#
121 psram type 4 psram_type04_17a0 july 30, 2004 preliminary write cycle (address latch type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for word operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw . 3. t cw is measured from the cs# going low to the end of write. 4. t bw is measured from the ub# and lb# going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter t wlrl is met. table 11.21. asynchronous write in synchronous mode ac characteristics notes: 1. address latch type, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.39. timing waveform of write cycle (address latch type) symbol speed units symbol speed units min max min max t adv 7 ? ns t bw 60 ? ns t as(a) 0 ? t wp 55 (note 2) ? t ah(a) 7 ? t wlrl 1 ? clock t css(a) 10 ? t as 0 ? ns t cw 60 ? t dw 30 ? t aw 60 ? t dh 0 ? we# data in t bw t wp t dh t dw data valid adv# address cs# valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high- z t wlrl 14 t aw t adv ub#, lb#
july 30, 2004 psram_type04_17a0 psram type 4 122 preliminary asynchronous write timing waveform in synchronous mode write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. low adv# type write cycle - we# controlled. 2. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect to the write operation if the parameter t wlrl is met. ta b l e 1 1 . 2 2 . asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.40. timing waveform of write cycle (low adv# type) symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1 ? clock t cw 60 ? t as 0 ? ns t aw 60 ? t wr 0 ? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0 ? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high- z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl ub#, lb#
123 psram type 4 psram_type04_17a0 july 30, 2004 preliminary write cycle (low adv# type) mrs# = v ih , oe# = v ih , wait# = high-z, ub# & lb# controlled notes: 1. low adv# type write cycle - ub# and lb# controlled. 2. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect to the write operation if the parameter t wlrl is met. ta b l e 1 1 . 2 3 . asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, ub#, lb# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.41. timing waveform of write cycle (low adv# type) symbol speed units symbol speed units min max min max t wc 70 ? ns t wlrl 1 ? clock t cw 60 ? t as 0 ? ns t aw 60 ? t wr 0 ? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0 ? address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high- z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z ub#, lb#
july 30, 2004 psram_type04_17a0 psram type 4 124 preliminary multiple write cycle (low adv# type) mrse = v ih , oe# = v ih , wait# = high-z, we# controlled notes: 1. low adv# type multiple write cycle. 2. a write occurs during the overlap (t wp ) of low cs# and low we#. a write begins when cs# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs# goes high or we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the cs# going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs# or we# going high. 6. clock input does not have any affect on the asynchronous multiple write operation if t whp is shorter than the (read latency - 1) clock duration. 7. t wp(min) = 70ns for continuous write operation over 50 times. figure 11.42. timing waveform of multiple write cycle (low adv# type) address data valid we# data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs# adv# data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw 14 ub#, lb#
125 psram type 4 psram_type04_17a0 july 30, 2004 preliminary ta b l e 1 1 . 2 4 . asynchronous write in synchronous mode ac characteristics notes: 1. low adv# type multiple write, we# controlled. 2. t wp(min) = 70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 ? ns t whp 5ns latency-1 clock ? t cw 60 ? t as 0? ns t aw 60 ? t wr 0? t bw 60 ? t dw 30 ? t wp 55 (note 2) ? t dh 0?
july 30, 2004 psram_type04_17a0 psram type 4 126 preliminary ac operating conditions test conditions (test load and test input/output reference) ? input pulse level: 0.2 to v cc -0.2v ? input rising and falling time: 3ns ? input and output reference voltage: 0.5 x v cc ? output load (see figure 11.34 ): cl = 30pf figure 11.43. ac output load circuit 50 ? dout 30pf z0= 50 ? vtt = 0.5 x v ddq
127 psram type 4 psram_type04_17a0 july 30, 2004 preliminary table 11.25. synchronous ac characteristics note: (v cc = 1.7~2.0v, ta=-40 to 85 c, maximum main clock frequency = 66mhz. parameter list symbol speed units min max burst operation (common) clock cycle time t 15 200 ns burst cycle time t bc ? 2500 address set-up time to adv# falling (burst) t as(b) 0? address hold time from adv# rising (burst) t ah(b) 7? adv# setup time t advs 5? adv# hold time t advh 7? cs# setup time to clock rising (burst) t css(b) 5? burst end to new adv# falling t beadv 7? burst stop to new adv# falling t bsadv 12 ? cs# low hold time from clock t cslh 7? cs# high pulse width t cshp 55 ? adv# high pulse width t adhp ?? chip select to wait# low t wl ?10 adv# falling to wait# low t awl ?10 clock to wait# high t wh ?12 chip de-select to wait# high-z t wz ?7 burst read operation ub#, lb# enable to end of latency clock t bel 1?clock output enable to end of latency clock t oel 1?clock ub#, lb# valid to low-z output t blz 5? ns output enable to low-z output t olz 5? latency clock rising edge to data output t cd ?10 output hold t oh 3? burst end clock to output high-z t hz ?10 chip de-select to output high-z t chz ?7 output disable to output high-z t ohz ?7 ub#, lb# disable to output high-z t bhz ?7 burst write operation we# set-up time to command clock t wes 5 ? ns we# hold time from command clock t weh 5 ? we# high pulse width t whp 5 ? ub#, lb# set-up time to clock t bs 5 ? ub#, lb# hold time from clock t bh 5 ? byte masking set-up time to clock t bms 7 ? byte masking hold time from clock t bmh 7 ? data set-up time to clock t ds 5 ? data hold time from clock t dhc 3 ?
july 30, 2004 psram_type04_17a0 psram type 4 128 preliminary synchronous burst operation timing waveform latency = 5, burst length = 4 (mrs# = v ih ) ta b l e 1 1 . 2 6 . burst operation ac characteristics figure 11.44. timing waveform of basic burst operation symbol speed units symbol speed units min max min max t 15 200 ns t as(b) 0 ? ns t bc ? 2500 t ah(b) 7 ? t advs 5 ? t css(b) 5 ? t advh 7 ? t beadv 7 ? 123456789101112131415 adv# address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 data in d0 d1 d3 d0 d2 t beadv burst write end clock cs# t css(b) t bc undefined
129 psram type 4 psram_type04_17a0 july 30, 2004 preliminary synchronous burst read timing waveform read timings latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# toggling consecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. figure 11.45. timing waveform of burst read cycle (1) 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t beadv t bc lb#, ub# undefined
july 30, 2004 psram_type04_17a0 psram type 4 130 preliminary ta b l e 1 1 . 2 7 . burst read ac characteristics latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). cs# low holding consecutive burst read notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. the consecutive multiple burst read operation with holding cs# low is possible only through issuing a new adv# and address. 5. burst cycle time (t bc ) should not be over 2.5s. symbol speed units symbol speed units min max min max t cshp 5 ? ns t ohz ? 7 ns t bel 1 ? clock t bhz ? 7 t oel 1 ? t cd ? 10 t blz 5 ? ns t oh 3 ? t olz 5 ? t wl ? 10 t hz ? 10 t wh ? 12 t chz ? 7 t wz ? 7 figure 11.46. timing waveform of burst read cycle (2) 123456789101112131415 adv# address cs# data out oe# clk dq0 dq1 dq2 dq3 t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh t beadv t bc lb#, ub# undefined
131 psram type 4 psram_type04_17a0 july 30, 2004 preliminary ta b l e 1 1 . 2 8 . burst read ac characteristics latency = 5, burst length = 4, wp = low enable (we# = v ih , mrs# = v ih ). last data sustaining notes: 1. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge). 2. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 3. burst cycle time (t bc ) should not be over 2.5s. symbol speed units symbol speed units min max min max t bel 1 ? clock t cd ? 10 ns t oel 1 ? t oh 3 ? t blz 5 ? ns t wl ? 10 t olz 5 ? t awl ? 10 t hz ? 10 t wh ? 12 figure 11.47. timing waveform of burst read cycle (3) adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t c are dq3 1234567891011121314 t bel t oel t blz t olz wait# high-z 0 t wl t wh t bc lb#, ub# undefined
july 30, 2004 psram_type04_17a0 psram type 4 132 preliminary ta b l e 1 1 . 2 9 . burst read ac characteristics symbol speed units symbol speed units min max min max t bel 1 ? clock t cd ? 10 ns t oel 1 ? t oh 3 ? t blz 5 ? ns t wl ? 10 t olz 5 ? t awl ? 12
133 psram type 4 psram_type04_17a0 july 30, 2004 preliminary write timings latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# toggling consecutive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. burst cycle time (t bc ) should not be over 2.5s. figure 11.48. timing waveform of burst write cycle (1) 12345678910111213 adv# address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh t beadv t bc lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 134 preliminary table 11.30. burst write ac characteristics symbol speed units symbol speed units min max min max t cshp 5 ? ns t whp 5 ? ns t bs 5 ? t ds 5 ? t bh 5 ? t dhc 3 ? t bms 7 ? t wl ? 10 t bmh 7 ? t wh ? 12 t wes 5 ? t wz ? 7 t weh 5 ?
135 psram type 4 psram_type04_17a0 july 30, 2004 preliminary latency = 5, burst length = 4, wp = low enable (oe# = v ih , mrs# = v ih ). cs# low holding consecutive burst write notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 3. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 4. d2 is masked by ub# and lb#. 5. the consecutive multiple burst read operation with holding cs# low is possible only through issuing a new adv# and address. 6. burst cycle time (t bc ) should not be over 2.5s. table 11.31. burst write ac characteristics figure 11.49. timing waveform of burst write cycle (2) symbol speed units symbol speed units min max min max t bs 5? ns t whp 5? ns t bh 5? t ds 5? t bms 7? t dhc 3? t bmh 7? t wl ?10 t wes 5? t awl ?10 t weh 5? t wh ?12 12345678910111213 adv address cs# data in we# clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds t dhc don?t ca re t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t awl latency 5 valid valid t wh t beadv t bc lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 136 preliminary synchronous burst read stop timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. ta b l e 1 1 . 3 2 . burst read stop ac characteristics figure 11.50. timing waveform of burst read stop by cs# symbol speed units symbol speed units min max min max t bsadv 12 ? ns t cd ?10 ns t cslh 7? t oh 3? t cshp 5? t chz ?7 t bel 1? clock t wl ?10 t oel 1? t wh ?12 t blz 5? ns t wz ?7 t olz 5? 1234567891011121314 adv# address cs# data oe# clk dq0 t cd don?t c are valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz wait# t bel t oel t blz t olz t cslh t cshp high-z 0 high- z t wl t wh t wz t wl dq1 t bsadv lb#, ub# undefined
137 psram type 4 psram_type04_17a0 july 30, 2004 preliminary synchronous burst write stop timing waveform latency = 5, burst length = 4, wp = low enable (oe#= v ih , mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5s. table 11.33. burst write stop ac characteristics figure 11.51. timing waveform of burst write stop by cs# symbol speed units symbol speed units min max min max t bsadv 12 ? ns t whp 5? ns t cslh 7? t ds 5? t cshp 5? t dhc 3? t bs 5? t wl ?10 t bh 5? t wh ?12 t wes 5? t wz ?7 t weh 5? 12345678910111213 adv# address cs# data in we# clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc wait# 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t ca re t whp t bsadv t bs t bh lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 138 preliminary synchronous burst read suspend timing waveform latency = 5, burst length = 4, wp = low enable (we#= v ih , mrs# = v ih ). notes: 1. if the clock input is halted during burst read operation, the data output will be suspended. during the burst read suspend period, oe# high drives data output to high-z. if the clock input is resumed, the suspended data will be output first. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. during the suspend period, oe# high drives dq to high-z and oe# low drives dq to low-z. if oe# stays low during suspend period, the previous data will be sustained. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 4 . burst read suspend ac characteristics figure 11.52. timing waveform of burst read suspend cycle (1) symbol speed units symbol speed units min max min max t bel 1? clock t hz ?10 ns t oel 1? t ohz ?7 t blz 5? ns t wl ?10 t olz 5? t wh ?12 t cd ?10 t wz ?7 t oh 3? 123456 7891 011 adv# address cs# data out oe# clk dq0 dq1 dq2 t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care wait# t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc t oh lb#, ub# undefined
139 psram type 4 psram_type04_17a0 july 30, 2004 preliminary transition timing waveform between read and write latency = 5, burst length = 4, wp = low enable (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 5 . burst read to asynchronous write (address latch type) ac characteristics latency = 5, burst length = 4 (mrs# = v ih ). figure 11.53. synchronous burst read to asynchronous write (address latch type) symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we# t css(a) data in t dh t dw data valid high- z high-z t as(a) t ah(a) t beadv t as read laten cy 5 0 t wp t wlrl t cw t aw t bw t bc wait# high-z t wh t wl t wz high-z t adv lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 140 preliminary notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 6 . burst read to asynchronous write (low adv# type) ac characteristics figure 11.54. synchronous burst read to asynchronous write (low adv# type) symbol speed units symbol speed units min max min max t beadv 7?nst wlrl 1?clock 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t ca re t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we# data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw t as t wr valid addr ess read late ncy 5 t wlrl wait# high-z t wh t wl t wz dq3 t bc high-z lb#, ub#
141 psram type 4 psram_type04_17a0 july 30, 2004 preliminary latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 7 . asynchronous write (address latch type) to burst read ac characteristics figure 11.55. asynchronous write (address latch type) to synchronous burst read timing symbol speed units symbol speed units min max min max t wlrl 1?clock 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t wp t bw t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw t adv t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 142 preliminary latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 8 . asynchronous write (low adv# type) to burst read ac characteristics figure 11.56. asynchronous write (low adv# type) to synchronous burst read timing symbol speed units symbol speed units min max min max t wlrl 1?clockt adhp ?ns 12345678910111213 1920 adv# address cs# data out oe# clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we# t css(b) data in high- z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp read latenc y 5 t wlrl wait# high- z t wh t wl t wz t bc lb#, ub#
143 psram type 4 psram_type04_17a0 july 30, 2004 preliminary latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 3 9 . asynchronous write (low adv# type) to burst read ac characteristics figure 11.57. synchronous burst read to synchronous burst write timing symbol speed units symbol speed units min max min max t beadv 7?ns high- z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we# t css(b) data in high- z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait# t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh lb#, ub#
july 30, 2004 psram_type04_17a0 psram type 4 144 preliminary latency = 5, burst length = 4 (mrs# = v ih ). notes: 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, t beadv should be met. 2. /wait low (t wl or t awl ): data not available (driven by cs# low going edge or adv# low going edge) /wait high (t wh ): data available (driven by latency-1 clock) /wait high-z (t wz ): data don?t care (driven by cs# high going edge) 3. multiple clock risings are allowed during low adv# period. the burst operation starts from the first clock rising. 4. burst cycle time (t bc ) should not be over 2.5s. ta b l e 1 1 . 4 0 . asynchronous write (low adv# type) to burst read ac characteristics figure 11.58. synchronous burst write to synchronous burst read timing symbol speed units symbol speed units min max min max t beadv 7?ns high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv# address cs# data out oe# clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we# t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait# t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh d3 d0 dq0 dq1 dq3 dq2 high- z lb#, ub#
november 8, 2004 s71ws512/256nx0_ut s71ws512nx0/s71ws256nx0 146 preliminary revision summary revision a0 (november 8, 2004) initial release. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men - tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2003 -2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressfl ash are trademarks of span - sion llc. other company and product names used in this publication are for identification purposes only and may be trademarks o f their respective compa - nies.

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